board/isee/igep00x0/igep00x0.c

   1 /*
   2  * (C) Copyright 2010
   3  * ISEE 2007 SL, <www.iseebcn.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <common.h>
   8 #include <status_led.h>
   9 #include <dm.h>
  10 #include <ns16550.h>
  11 #include <twl4030.h>
  12 #include <netdev.h>
  13 #include <asm/gpio.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/mem.h>
  16 #include <asm/arch/mmc_host_def.h>
  17 #include <asm/arch/mux.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/mach-types.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/nand.h>
  22 #include <linux/mtd/onenand.h>
  23 #include <jffs2/load_kernel.h>
  24 #include "igep00x0.h"
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 const omap3_sysinfo sysinfo = {
  29         DDR_STACKED,
  30 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
  31         "IGEPv2",
  32 #endif
  33 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
  34         "IGEP COM MODULE/ELECTRON",
  35 #endif
  36 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
  37         "IGEP COM PROTON",
  38 #endif
  39 #if defined(CONFIG_ENV_IS_IN_ONENAND)
  40         "ONENAND",
  41 #else
  42         "NAND",
  43 #endif
  44 };
  45
  46 static const struct ns16550_platdata igep_serial = {
  47         .base = OMAP34XX_UART3,
  48         .reg_shift = 2,
  49         .clock = V_NS16550_CLK
  50 };
  51
  52 U_BOOT_DEVICE(igep_uart) = {
  53         "ns16550_serial",
  54         &igep_serial
  55 };
  56
  57 /*
  58  * Routine: board_init
  59  * Description: Early hardware init.
  60  */
  61 int board_init(void)
  62 {
  63         int loops = 100;
  64
  65         /* find out flash memory type, assume NAND first */
  66         gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
  67         gpmc_init();
  68
  69         /* Issue a RESET and then READID */
  70         writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
  71         writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
  72         while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
  73                                                 != NAND_STATUS_READY) {
  74                 udelay(1);
  75                 if (--loops == 0) {
  76                         gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
  77                         gpmc_init();    /* reinitialize for OneNAND */
  78                         break;
  79                 }
  80         }
  81
  82         /* boot param addr */
  83         gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  84
  85 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
  86         status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
  87 #endif
  88
  89         return 0;
  90 }
  91
  92 #ifdef CONFIG_SPL_BUILD
  93 /*
  94  * Routine: get_board_mem_timings
  95  * Description: If we use SPL then there is no x-loader nor config header
  96  * so we have to setup the DDR timings ourself on both banks.
  97  */
  98 void get_board_mem_timings(struct board_sdrc_timings *timings)
  99 {
 100         int mfr, id, err = identify_nand_chip(&mfr, &id);
 101
 102         timings->mr = MICRON_V_MR_165;
 103         if (!err && mfr == NAND_MFR_MICRON) {
 104                 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
 105                 timings->ctrla = MICRON_V_ACTIMA_200;
 106                 timings->ctrlb = MICRON_V_ACTIMB_200;
 107                 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 108                 gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
 109         } else {
 110                 if (get_cpu_family() == CPU_OMAP34XX) {
 111                         timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
 112                         timings->ctrla = NUMONYX_V_ACTIMA_165;
 113                         timings->ctrlb = NUMONYX_V_ACTIMB_165;
 114                         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 115                 } else {
 116                         timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
 117                         timings->ctrla = NUMONYX_V_ACTIMA_200;
 118                         timings->ctrlb = NUMONYX_V_ACTIMB_200;
 119                         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 120                 }
 121                 gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
 122         }
 123 }
 124 #endif
 125
 126 int onenand_board_init(struct mtd_info *mtd)
 127 {
 128         if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
 129                 struct onenand_chip *this = mtd->priv;
 130                 this->base = (void *)CONFIG_SYS_ONENAND_BASE;
 131                 return 0;
 132         }
 133         return 1;
 134 }
 135
 136 #if defined(CONFIG_CMD_NET)
 137 static void reset_net_chip(int gpio)
 138 {
 139         if (!gpio_request(gpio, "eth nrst")) {
 140                 gpio_direction_output(gpio, 1);
 141                 udelay(1);
 142                 gpio_set_value(gpio, 0);
 143                 udelay(40);
 144                 gpio_set_value(gpio, 1);
 145                 mdelay(10);
 146         }
 147 }
 148
 149 /*
 150  * Routine: setup_net_chip
 151  * Description: Setting up the configuration GPMC registers specific to the
 152  *              Ethernet hardware.
 153  */
 154 static void setup_net_chip(void)
 155 {
 156         struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 157         static const u32 gpmc_lan_config[] = {
 158                 NET_LAN9221_GPMC_CONFIG1,
 159                 NET_LAN9221_GPMC_CONFIG2,
 160                 NET_LAN9221_GPMC_CONFIG3,
 161                 NET_LAN9221_GPMC_CONFIG4,
 162                 NET_LAN9221_GPMC_CONFIG5,
 163                 NET_LAN9221_GPMC_CONFIG6,
 164         };
 165
 166         enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
 167                         CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
 168
 169         /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 170         writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
 171         /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
 172         writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
 173         /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
 174         writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
 175                 &ctrl_base->gpmc_nadv_ale);
 176
 177         reset_net_chip(64);
 178 }
 179
 180 int board_eth_init(bd_t *bis)
 181 {
 182 #ifdef CONFIG_SMC911X
 183         return smc911x_initialize(0, CONFIG_SMC911X_BASE);
 184 #else
 185         return 0;
 186 #endif
 187 }
 188 #else
 189 static inline void setup_net_chip(void) {}
 190 #endif
 191
 192 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 193 int board_mmc_init(bd_t *bis)
 194 {
 195         return omap_mmc_init(0, 0, 0, -1, -1);
 196 }
 197 #endif
 198
 199 #if defined(CONFIG_GENERIC_MMC)
 200 void board_mmc_power_init(void)
 201 {
 202         twl4030_power_mmc_init(0);
 203 }
 204 #endif
 205
 206 void set_fdt(void)
 207 {
 208         switch (gd->bd->bi_arch_number) {
 209         case MACH_TYPE_IGEP0020:
 210                 setenv("fdtfile", "omap3-igep0020.dtb");
 211                 break;
 212         case MACH_TYPE_IGEP0030:
 213                 setenv("fdtfile", "omap3-igep0030.dtb");
 214                 break;
 215         }
 216 }
 217
 218 /*
 219  * Routine: misc_init_r
 220  * Description: Configure board specific parts
 221  */
 222 int misc_init_r(void)
 223 {
 224         twl4030_power_init();
 225
 226         setup_net_chip();
 227
 228         omap_die_id_display();
 229
 230         set_fdt();
 231
 232         return 0;
 233 }
 234
 235 /*
 236  * Routine: set_muxconf_regs
 237  * Description: Setting up the configuration Mux registers specific to the
 238  *              hardware. Many pins need to be moved from protect to primary
 239  *              mode.
 240  */
 241 void set_muxconf_regs(void)
 242 {
 243         MUX_DEFAULT();
 244
 245 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
 246         MUX_IGEP0020();
 247 #endif
 248
 249 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
 250         MUX_IGEP0030();
 251 #endif
 252 }