board/isee/igep00x0/igep00x0.c

   1 /*
   2  * (C) Copyright 2010
   3  * ISEE 2007 SL, <www.iseebcn.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <common.h>
   8 #include <status_led.h>
   9 #include <dm.h>
  10 #include <ns16550.h>
  11 #include <twl4030.h>
  12 #include <netdev.h>
  13 #include <spl.h>
  14 #include <asm/gpio.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/mem.h>
  17 #include <asm/arch/mmc_host_def.h>
  18 #include <asm/arch/mux.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/mach-types.h>
  21 #include <linux/mtd/mtd.h>
  22 #include <linux/mtd/nand.h>
  23 #include <linux/mtd/nand.h>
  24 #include <linux/mtd/onenand.h>
  25 #include <jffs2/load_kernel.h>
  26 #include <mtd_node.h>
  27 #include <fdt_support.h>
  28 #include "igep00x0.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 static const struct ns16550_platdata igep_serial = {
  33         .base = OMAP34XX_UART3,
  34         .reg_shift = 2,
  35         .clock = V_NS16550_CLK,
  36         .fcr = UART_FCR_DEFVAL,
  37 };
  38
  39 U_BOOT_DEVICE(igep_uart) = {
  40         "ns16550_serial",
  41         &igep_serial
  42 };
  43
  44 /*
  45  * Routine: board_init
  46  * Description: Early hardware init.
  47  */
  48 int board_init(void)
  49 {
  50         int loops = 100;
  51
  52         /* find out flash memory type, assume NAND first */
  53         gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
  54         gpmc_init();
  55
  56         /* Issue a RESET and then READID */
  57         writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
  58         writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
  59         while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
  60                                                 != NAND_STATUS_READY) {
  61                 udelay(1);
  62                 if (--loops == 0) {
  63                         gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
  64                         gpmc_init();    /* reinitialize for OneNAND */
  65                         break;
  66                 }
  67         }
  68
  69         /* boot param addr */
  70         gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  71
  72 #if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
  73         status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
  74 #endif
  75
  76         return 0;
  77 }
  78
  79 #ifdef CONFIG_SPL_BUILD
  80 /*
  81  * Routine: get_board_mem_timings
  82  * Description: If we use SPL then there is no x-loader nor config header
  83  * so we have to setup the DDR timings ourself on both banks.
  84  */
  85 void get_board_mem_timings(struct board_sdrc_timings *timings)
  86 {
  87         int mfr, id, err = identify_nand_chip(&mfr, &id);
  88
  89         timings->mr = MICRON_V_MR_165;
  90         if (!err) {
  91                 switch (mfr) {
  92                 case NAND_MFR_HYNIX:
  93                         timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
  94                         timings->ctrla = HYNIX_V_ACTIMA_200;
  95                         timings->ctrlb = HYNIX_V_ACTIMB_200;
  96                         break;
  97                 case NAND_MFR_MICRON:
  98                         timings->mcfg = MICRON_V_MCFG_200(256 << 20);
  99                         timings->ctrla = MICRON_V_ACTIMA_200;
 100                         timings->ctrlb = MICRON_V_ACTIMB_200;
 101                         break;
 102                 default:
 103                         /* Should not happen... */
 104                         break;
 105                 }
 106                 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 107                 gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
 108         } else {
 109                 if (get_cpu_family() == CPU_OMAP34XX) {
 110                         timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
 111                         timings->ctrla = NUMONYX_V_ACTIMA_165;
 112                         timings->ctrlb = NUMONYX_V_ACTIMB_165;
 113                         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 114                 } else {
 115                         timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
 116                         timings->ctrla = NUMONYX_V_ACTIMA_200;
 117                         timings->ctrlb = NUMONYX_V_ACTIMB_200;
 118                         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 119                 }
 120                 gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
 121         }
 122 }
 123
 124 #ifdef CONFIG_SPL_OS_BOOT
 125 int spl_start_uboot(void)
 126 {
 127         /* break into full u-boot on 'c' */
 128         if (serial_tstc() && serial_getc() == 'c')
 129                 return 1;
 130
 131         return 0;
 132 }
 133 #endif
 134 #endif
 135
 136 int onenand_board_init(struct mtd_info *mtd)
 137 {
 138         if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
 139                 struct onenand_chip *this = mtd->priv;
 140                 this->base = (void *)CONFIG_SYS_ONENAND_BASE;
 141                 return 0;
 142         }
 143         return 1;
 144 }
 145
 146 #if defined(CONFIG_CMD_NET)
 147 static void reset_net_chip(int gpio)
 148 {
 149         if (!gpio_request(gpio, "eth nrst")) {
 150                 gpio_direction_output(gpio, 1);
 151                 udelay(1);
 152                 gpio_set_value(gpio, 0);
 153                 udelay(40);
 154                 gpio_set_value(gpio, 1);
 155                 mdelay(10);
 156         }
 157 }
 158
 159 /*
 160  * Routine: setup_net_chip
 161  * Description: Setting up the configuration GPMC registers specific to the
 162  *              Ethernet hardware.
 163  */
 164 static void setup_net_chip(void)
 165 {
 166         struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 167         static const u32 gpmc_lan_config[] = {
 168                 NET_LAN9221_GPMC_CONFIG1,
 169                 NET_LAN9221_GPMC_CONFIG2,
 170                 NET_LAN9221_GPMC_CONFIG3,
 171                 NET_LAN9221_GPMC_CONFIG4,
 172                 NET_LAN9221_GPMC_CONFIG5,
 173                 NET_LAN9221_GPMC_CONFIG6,
 174         };
 175
 176         enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
 177                         CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
 178
 179         /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 180         writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
 181         /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
 182         writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
 183         /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
 184         writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
 185                 &ctrl_base->gpmc_nadv_ale);
 186
 187         reset_net_chip(64);
 188 }
 189
 190 int board_eth_init(bd_t *bis)
 191 {
 192 #ifdef CONFIG_SMC911X
 193         return smc911x_initialize(0, CONFIG_SMC911X_BASE);
 194 #else
 195         return 0;
 196 #endif
 197 }
 198 #else
 199 static inline void setup_net_chip(void) {}
 200 #endif
 201
 202 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 203 int board_mmc_init(bd_t *bis)
 204 {
 205         return omap_mmc_init(0, 0, 0, -1, -1);
 206 }
 207 #endif
 208
 209 #if defined(CONFIG_GENERIC_MMC)
 210 void board_mmc_power_init(void)
 211 {
 212         twl4030_power_mmc_init(0);
 213 }
 214 #endif
 215
 216 #ifdef CONFIG_OF_BOARD_SETUP
 217 int ft_board_setup(void *blob, bd_t *bd)
 218 {
 219 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 220         static struct node_info nodes[] = {
 221                 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
 222                 { "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, },
 223         };
 224
 225         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 226 #endif
 227         return 0;
 228 }
 229 #endif
 230
 231 void set_fdt(void)
 232 {
 233         switch (gd->bd->bi_arch_number) {
 234         case MACH_TYPE_IGEP0020:
 235                 setenv("fdtfile", "omap3-igep0020.dtb");
 236                 break;
 237         case MACH_TYPE_IGEP0030:
 238                 setenv("fdtfile", "omap3-igep0030.dtb");
 239                 break;
 240         }
 241 }
 242
 243 /*
 244  * Routine: misc_init_r
 245  * Description: Configure board specific parts
 246  */
 247 int misc_init_r(void)
 248 {
 249         twl4030_power_init();
 250
 251         setup_net_chip();
 252
 253         omap_die_id_display();
 254
 255         set_fdt();
 256
 257         return 0;
 258 }
 259
 260 void board_mtdparts_default(const char **mtdids, const char **mtdparts)
 261 {
 262         struct mtd_info *mtd = get_mtd_device(NULL, 0);
 263         if (mtd) {
 264                 static char ids[24];
 265                 static char parts[48];
 266                 const char *linux_name = "omap2-nand";
 267                 if (strncmp(mtd->name, "onenand0", 8) == 0)
 268                         linux_name = "omap2-onenand";
 269                 snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
 270                 snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
 271                          linux_name, 4 * mtd->erasesize >> 10);
 272                 *mtdids = ids;
 273                 *mtdparts = parts;
 274         }
 275 }
 276
 277 /*
 278  * Routine: set_muxconf_regs
 279  * Description: Setting up the configuration Mux registers specific to the
 280  *              hardware. Many pins need to be moved from protect to primary
 281  *              mode.
 282  */
 283 void set_muxconf_regs(void)
 284 {
 285         MUX_DEFAULT();
 286
 287 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
 288         MUX_IGEP0020();
 289 #endif
 290
 291 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
 292         MUX_IGEP0030();
 293 #endif
 294 }