3 * ISEE 2007 SL, <www.iseebcn.com>
5 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/mem.h>
15 #include <asm/arch/mmc_host_def.h>
16 #include <asm/arch/mux.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/mach-types.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 #if defined(CONFIG_CMD_NET)
24 /* GPMC definitions for LAN9221 chips */
25 static const u32 gpmc_lan_config[] = {
26 NET_LAN9221_GPMC_CONFIG1,
27 NET_LAN9221_GPMC_CONFIG2,
28 NET_LAN9221_GPMC_CONFIG3,
29 NET_LAN9221_GPMC_CONFIG4,
30 NET_LAN9221_GPMC_CONFIG5,
31 NET_LAN9221_GPMC_CONFIG6,
35 static const struct ns16550_platdata igep_serial = {
41 U_BOOT_DEVICE(igep_uart) = {
48 * Description: Early hardware init.
52 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
54 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
59 #if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD)
60 void show_boot_progress(int val)
63 /* something went wrong */
67 if (!gpio_request(IGEP00X0_GPIO_LED, ""))
68 gpio_direction_output(IGEP00X0_GPIO_LED, 1);
72 #ifdef CONFIG_SPL_BUILD
74 * Routine: omap_rev_string
75 * Description: For SPL builds output board rev
77 void omap_rev_string(void)
82 * Routine: get_board_mem_timings
83 * Description: If we use SPL then there is no x-loader nor config header
84 * so we have to setup the DDR timings ourself on both banks.
86 void get_board_mem_timings(struct board_sdrc_timings *timings)
88 timings->mr = MICRON_V_MR_165;
89 #ifdef CONFIG_BOOT_NAND
90 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
91 timings->ctrla = MICRON_V_ACTIMA_200;
92 timings->ctrlb = MICRON_V_ACTIMB_200;
93 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
95 if (get_cpu_family() == CPU_OMAP34XX) {
96 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
97 timings->ctrla = NUMONYX_V_ACTIMA_165;
98 timings->ctrlb = NUMONYX_V_ACTIMB_165;
99 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
102 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
103 timings->ctrla = NUMONYX_V_ACTIMA_200;
104 timings->ctrlb = NUMONYX_V_ACTIMB_200;
105 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
111 #if defined(CONFIG_CMD_NET)
113 * Routine: setup_net_chip
114 * Description: Setting up the configuration GPMC registers specific to the
117 static void setup_net_chip(void)
119 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
121 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
124 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
125 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
126 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
127 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
128 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
129 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
130 &ctrl_base->gpmc_nadv_ale);
132 /* Make GPIO 64 as output pin and send a magic pulse through it */
133 if (!gpio_request(64, "")) {
134 gpio_direction_output(64, 0);
135 gpio_set_value(64, 1);
137 gpio_set_value(64, 0);
139 gpio_set_value(64, 1);
143 static inline void setup_net_chip(void) {}
146 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
147 int board_mmc_init(bd_t *bis)
149 return omap_mmc_init(0, 0, 0, -1, -1);
155 switch (gd->bd->bi_arch_number) {
156 case MACH_TYPE_IGEP0020:
157 setenv("dtbfile", "omap3-igep0020.dtb");
159 case MACH_TYPE_IGEP0030:
160 setenv("dtbfile", "omap3-igep0030.dtb");
166 * Routine: misc_init_r
167 * Description: Configure board specific parts
169 int misc_init_r(void)
171 twl4030_power_init();
183 * Routine: set_muxconf_regs
184 * Description: Setting up the configuration Mux registers specific to the
185 * hardware. Many pins need to be moved from protect to primary
188 void set_muxconf_regs(void)
192 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
196 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
201 #if defined(CONFIG_CMD_NET)
202 int board_eth_init(bd_t *bis)
205 #ifdef CONFIG_SMC911X
206 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);