3 * ISEE 2007 SL, <www.iseebcn.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/omap_gpmc.h>
13 #include <asm/arch/mem.h>
14 #include <asm/arch/mmc_host_def.h>
15 #include <asm/arch/mux.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/mach-types.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 #if defined(CONFIG_CMD_NET)
23 /* GPMC definitions for LAN9221 chips */
24 static const u32 gpmc_lan_config[] = {
25 NET_LAN9221_GPMC_CONFIG1,
26 NET_LAN9221_GPMC_CONFIG2,
27 NET_LAN9221_GPMC_CONFIG3,
28 NET_LAN9221_GPMC_CONFIG4,
29 NET_LAN9221_GPMC_CONFIG5,
30 NET_LAN9221_GPMC_CONFIG6,
36 * Description: Early hardware init.
40 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
42 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
47 #if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD)
48 void show_boot_progress(int val)
51 /* something went wrong */
55 if (!gpio_request(IGEP00X0_GPIO_LED, ""))
56 gpio_direction_output(IGEP00X0_GPIO_LED, 1);
60 #ifdef CONFIG_SPL_BUILD
62 * Routine: omap_rev_string
63 * Description: For SPL builds output board rev
65 void omap_rev_string(void)
70 * Routine: get_board_mem_timings
71 * Description: If we use SPL then there is no x-loader nor config header
72 * so we have to setup the DDR timings ourself on both banks.
74 void get_board_mem_timings(struct board_sdrc_timings *timings)
76 timings->mr = MICRON_V_MR_165;
77 #ifdef CONFIG_BOOT_NAND
78 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
79 timings->ctrla = MICRON_V_ACTIMA_200;
80 timings->ctrlb = MICRON_V_ACTIMB_200;
81 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
83 if (get_cpu_family() == CPU_OMAP34XX) {
84 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
85 timings->ctrla = NUMONYX_V_ACTIMA_165;
86 timings->ctrlb = NUMONYX_V_ACTIMB_165;
87 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
90 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
91 timings->ctrla = NUMONYX_V_ACTIMA_200;
92 timings->ctrlb = NUMONYX_V_ACTIMB_200;
93 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
99 #if defined(CONFIG_CMD_NET)
101 * Routine: setup_net_chip
102 * Description: Setting up the configuration GPMC registers specific to the
105 static void setup_net_chip(void)
107 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
109 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
112 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
113 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
114 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
115 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
116 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
117 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
118 &ctrl_base->gpmc_nadv_ale);
120 /* Make GPIO 64 as output pin and send a magic pulse through it */
121 if (!gpio_request(64, "")) {
122 gpio_direction_output(64, 0);
123 gpio_set_value(64, 1);
125 gpio_set_value(64, 0);
127 gpio_set_value(64, 1);
131 static inline void setup_net_chip(void) {}
134 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
135 int board_mmc_init(bd_t *bis)
137 return omap_mmc_init(0, 0, 0, -1, -1);
143 switch (gd->bd->bi_arch_number) {
144 case MACH_TYPE_IGEP0020:
145 setenv("dtbfile", "omap3-igep0020.dtb");
147 case MACH_TYPE_IGEP0030:
148 setenv("dtbfile", "omap3-igep0030.dtb");
154 * Routine: misc_init_r
155 * Description: Configure board specific parts
157 int misc_init_r(void)
159 twl4030_power_init();
171 * Routine: set_muxconf_regs
172 * Description: Setting up the configuration Mux registers specific to the
173 * hardware. Many pins need to be moved from protect to primary
176 void set_muxconf_regs(void)
180 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
184 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
189 #if defined(CONFIG_CMD_NET)
190 int board_eth_init(bd_t *bis)
193 #ifdef CONFIG_SMC911X
194 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);