board/isee/igep003x/board.c

   1 /*
   2  * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
   3  *
   4  * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <errno.h>
  11 #include <spl.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/omap.h>
  15 #include <asm/arch/ddr_defs.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/gpio.h>
  18 #include <asm/arch/mmc_host_def.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/io.h>
  21 #include <asm/emif.h>
  22 #include <asm/gpio.h>
  23 #include <i2c.h>
  24 #include <miiphy.h>
  25 #include <cpsw.h>
  26 #include <fdt_support.h>
  27 #include <mtd_node.h>
  28 #include <jffs2/load_kernel.h>
  29 #include <environment.h>
  30 #include "board.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 /* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
  35  * and control IGEP0034 green and red LEDs.
  36  * U-boot configures these pins as input pullup to detect board revision:
  37  * IGEP0034-LITE = 0b00
  38  * IGEP0034 (FULL) = 0b01
  39  * IGEP0033 = 0b1X
  40  */
  41 #define GPIO_GREEN_REVISION     27
  42 #define GPIO_RED_REVISION       26
  43
  44 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  45
  46 /*
  47  * Routine: get_board_revision
  48  * Description: Returns the board revision
  49  */
  50 static int get_board_revision(void)
  51 {
  52         int revision;
  53
  54         gpio_request(GPIO_GREEN_REVISION, "green_revision");
  55         gpio_direction_input(GPIO_GREEN_REVISION);
  56         revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
  57         gpio_free(GPIO_GREEN_REVISION);
  58
  59         gpio_request(GPIO_RED_REVISION, "red_revision");
  60         gpio_direction_input(GPIO_RED_REVISION);
  61         revision = revision + gpio_get_value(GPIO_RED_REVISION);
  62         gpio_free(GPIO_RED_REVISION);
  63
  64         return revision;
  65 }
  66
  67 #ifdef CONFIG_SPL_BUILD
  68 /* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
  69 static const struct ddr_data ddr3_igep0034_data = {
  70         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  71         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  72         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  73         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  74 };
  75
  76 static const struct ddr_data ddr3_igep0034_lite_data = {
  77         .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
  78         .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
  79         .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
  80         .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
  81 };
  82
  83 static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
  84         .cmd0csratio = MT41K256M16HA125E_RATIO,
  85         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  86
  87         .cmd1csratio = MT41K256M16HA125E_RATIO,
  88         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  89
  90         .cmd2csratio = MT41K256M16HA125E_RATIO,
  91         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  92 };
  93
  94 static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
  95         .cmd0csratio = K4B2G1646EBIH9_RATIO,
  96         .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  97
  98         .cmd1csratio = K4B2G1646EBIH9_RATIO,
  99         .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 100
 101         .cmd2csratio = K4B2G1646EBIH9_RATIO,
 102         .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 103 };
 104
 105 static struct emif_regs ddr3_igep0034_emif_reg_data = {
 106         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 107         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 108         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 109         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 110         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 111         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 112         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 113 };
 114
 115 static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
 116         .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
 117         .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
 118         .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
 119         .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
 120         .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
 121         .zq_config = K4B2G1646EBIH9_ZQ_CFG,
 122         .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
 123 };
 124
 125 const struct ctrl_ioregs ioregs_igep0034 = {
 126         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 127         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 128         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 129         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 130         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 131 };
 132
 133 const struct ctrl_ioregs ioregs_igep0034_lite = {
 134         .cm0ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 135         .cm1ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 136         .cm2ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 137         .dt0ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 138         .dt1ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 139 };
 140
 141 #define OSC    (V_OSCK/1000000)
 142 const struct dpll_params dpll_ddr = {
 143                 400, OSC-1, 1, -1, -1, -1, -1};
 144
 145 const struct dpll_params *get_dpll_ddr_params(void)
 146 {
 147         return &dpll_ddr;
 148 }
 149
 150 void set_uart_mux_conf(void)
 151 {
 152         enable_uart0_pin_mux();
 153 }
 154
 155 void set_mux_conf_regs(void)
 156 {
 157         enable_board_pin_mux();
 158 }
 159
 160 void sdram_init(void)
 161 {
 162         if (get_board_revision() == 1)
 163                 config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
 164                         &ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
 165         else
 166                 config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
 167                         &ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
 168 }
 169
 170 #ifdef CONFIG_SPL_OS_BOOT
 171 int spl_start_uboot(void)
 172 {
 173         /* break into full u-boot on 'c' */
 174         return serial_tstc() && serial_getc() == 'c';
 175 }
 176 #endif
 177 #endif
 178
 179 /*
 180  * Basic board specific setup.  Pinmux has been handled already.
 181  */
 182 int board_init(void)
 183 {
 184         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 185
 186         gpmc_init();
 187
 188         return 0;
 189 }
 190
 191 #ifdef CONFIG_BOARD_LATE_INIT
 192 int board_late_init(void)
 193 {
 194 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 195         switch (get_board_revision()) {
 196                 case 0:
 197                         setenv("board_name", "igep0034-lite");
 198                         break;
 199                 case 1:
 200                         setenv("board_name", "igep0034");
 201                         break;
 202                 default:
 203                         setenv("board_name", "igep0033");
 204                         break;
 205         }
 206 #endif
 207         return 0;
 208 }
 209 #endif
 210
 211 #ifdef CONFIG_OF_BOARD_SETUP
 212 int ft_board_setup(void *blob, bd_t *bd)
 213 {
 214 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 215         static struct node_info nodes[] = {
 216                 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
 217         };
 218
 219         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 220 #endif
 221         return 0;
 222 }
 223 #endif
 224
 225 #if defined(CONFIG_DRIVER_TI_CPSW)
 226 static void cpsw_control(int enabled)
 227 {
 228         /* VTP can be added here */
 229
 230         return;
 231 }
 232
 233 static struct cpsw_slave_data cpsw_slaves[] = {
 234         {
 235                 .slave_reg_ofs  = 0x208,
 236                 .sliver_reg_ofs = 0xd80,
 237                 .phy_addr       = 0,
 238                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 239         },
 240 };
 241
 242 static struct cpsw_platform_data cpsw_data = {
 243         .mdio_base              = CPSW_MDIO_BASE,
 244         .cpsw_base              = CPSW_BASE,
 245         .mdio_div               = 0xff,
 246         .channels               = 8,
 247         .cpdma_reg_ofs          = 0x800,
 248         .slaves                 = 1,
 249         .slave_data             = cpsw_slaves,
 250         .ale_reg_ofs            = 0xd00,
 251         .ale_entries            = 1024,
 252         .host_port_reg_ofs      = 0x108,
 253         .hw_stats_reg_ofs       = 0x900,
 254         .bd_ram_ofs             = 0x2000,
 255         .mac_control            = (1 << 5),
 256         .control                = cpsw_control,
 257         .host_port_num          = 0,
 258         .version                = CPSW_CTRL_VERSION_2,
 259 };
 260
 261 int board_eth_init(bd_t *bis)
 262 {
 263         int rv, ret = 0;
 264         uint8_t mac_addr[6];
 265         uint32_t mac_hi, mac_lo;
 266
 267         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 268                 /* try reading mac address from efuse */
 269                 mac_lo = readl(&cdev->macid0l);
 270                 mac_hi = readl(&cdev->macid0h);
 271                 mac_addr[0] = mac_hi & 0xFF;
 272                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 273                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 274                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 275                 mac_addr[4] = mac_lo & 0xFF;
 276                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 277                 if (is_valid_ethaddr(mac_addr))
 278                         eth_setenv_enetaddr("ethaddr", mac_addr);
 279         }
 280
 281         writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
 282                &cdev->miisel);
 283
 284         if (get_board_revision() == 1)
 285                 cpsw_slaves[0].phy_addr = 1;
 286
 287         rv = cpsw_register(&cpsw_data);
 288         if (rv < 0)
 289                 printf("Error %d registering CPSW switch\n", rv);
 290         else
 291                 ret += rv;
 292
 293         return ret;
 294 }
 295 #endif