3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
15 * Philippe Robin, <philippe.robin@arm.com>
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
42 void flash__init (void);
43 void ether__init (void);
44 void peripheral_power_enable (void);
46 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
47 void show_boot_progress(int progress)
49 printf("Boot reached stage %d\n", progress);
53 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
55 static inline void delay (unsigned long loops)
57 __asm__ volatile ("1:\n"
59 "bne 1b":"=r" (loops):"0" (loops));
63 * Miscellaneous platform dependent initialisations
68 DECLARE_GLOBAL_DATA_PTR;
70 /* arch number of Integrator Board */
71 gd->bd->bi_arch_number = 21;
73 /* adress of boot parameters */
74 gd->bd->bi_boot_params = 0x00000100;
83 int misc_init_r (void)
88 setenv("verify", "n");
93 * Initialize PCI Devices, report devices found.
97 #ifndef CONFIG_PCI_PNP
99 static struct pci_config_table pci_integrator_config_table[] = {
100 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
101 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
103 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
108 /* V3 access routines */
109 #define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
110 #define _V3Read16(o) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)))
112 #define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v))
113 #define _V3Read32(o) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)))
115 /* Compute address necessary to access PCI config space for the given */
116 /* bus and device. */
117 #define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({ \
118 unsigned int __address, __devicebit; \
119 unsigned short __mapaddress; \
120 unsigned int __dev = PCI_DEV (__devfn); /* FIXME to check!! (slot?) */ \
123 /* local bus segment so need a type 0 config cycle */ \
124 /* build the PCI configuration "address" with one-hot in A31-A11 */ \
125 __address = PCI_CONFIG_BASE; \
126 __address |= ((__devfn & 0x07) << 8); \
127 __address |= __offset & 0xFF; \
128 __mapaddress = 0x000A; /* 101=>config cycle, 0=>A1=A0=0 */ \
129 __devicebit = (1 << (__dev + 11)); \
131 if ((__devicebit & 0xFF000000) != 0) { \
132 /* high order bits are handled by the MAP register */ \
133 __mapaddress |= (__devicebit >> 16); \
135 /* low order bits handled directly in the address */ \
136 __address |= __devicebit; \
138 } else { /* bus !=0 */ \
139 /* not the local bus segment so need a type 1 config cycle */ \
140 /* A31-A24 are don't care (so clear to 0) */ \
141 __mapaddress = 0x000B; /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */ \
142 __address = PCI_CONFIG_BASE; \
143 __address |= ((__bus & 0xFF) << 16); /* bits 23..16 = bus number */ \
144 __address |= ((__dev & 0x1F) << 11); /* bits 15..11 = device number */ \
145 __address |= ((__devfn & 0x07) << 8); /* bits 10..8 = function number */ \
146 __address |= __offset & 0xFF; /* bits 7..0 = register number */ \
148 _V3Write16 (V3_LB_MAP1, __mapaddress); \
152 /* _V3OpenConfigWindow - open V3 configuration window */
153 #define _V3OpenConfigWindow() { \
154 /* Set up base0 to see all 512Mbytes of memory space (not */ \
155 /* prefetchable), this frees up base1 for re-use by configuration*/ \
158 _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \
159 0x90 | V3_LB_BASE_M_ENABLE)); \
160 /* Set up base1 to point into configuration space, note that MAP1 */ \
161 /* register is set up by pciMakeConfigAddress(). */ \
163 _V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) | \
164 0x40 | V3_LB_BASE_M_ENABLE)); \
167 /* _V3CloseConfigWindow - close V3 configuration window */
168 #define _V3CloseConfigWindow() { \
169 /* Reassign base1 for use by prefetchable PCI memory */ \
170 _V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) \
171 | 0x84 | V3_LB_BASE_M_ENABLE)); \
172 _V3Write16 (V3_LB_MAP1, \
173 (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006); \
175 /* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */ \
177 _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \
178 0x80 | V3_LB_BASE_M_ENABLE)); \
181 static int pci_integrator_read_byte (struct pci_controller *hose, pci_dev_t dev,
182 int offset, unsigned char *val)
184 _V3OpenConfigWindow ();
185 *val = *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
188 _V3CloseConfigWindow ();
193 static int pci_integrator_read__word (struct pci_controller *hose,
194 pci_dev_t dev, int offset,
197 _V3OpenConfigWindow ();
198 *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
201 _V3CloseConfigWindow ();
206 static int pci_integrator_read_dword (struct pci_controller *hose,
207 pci_dev_t dev, int offset,
210 _V3OpenConfigWindow ();
211 *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
214 *val |= (*(volatile unsigned int *)
215 PCI_CONFIG_ADDRESS (PCI_BUS (dev), PCI_FUNC (dev),
216 (offset + 2))) << 16;
217 _V3CloseConfigWindow ();
222 static int pci_integrator_write_byte (struct pci_controller *hose,
223 pci_dev_t dev, int offset,
226 _V3OpenConfigWindow ();
227 *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
230 _V3CloseConfigWindow ();
235 static int pci_integrator_write_word (struct pci_controller *hose,
236 pci_dev_t dev, int offset,
239 _V3OpenConfigWindow ();
240 *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
243 _V3CloseConfigWindow ();
248 static int pci_integrator_write_dword (struct pci_controller *hose,
249 pci_dev_t dev, int offset,
252 _V3OpenConfigWindow ();
253 *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
255 offset) = (val & 0xFFFF);
256 *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
258 (offset + 2)) = ((val >> 16) & 0xFFFF);
259 _V3CloseConfigWindow ();
263 /******************************
265 ******************************/
267 struct pci_controller integrator_hose = {
268 #ifndef CONFIG_PCI_PNP
269 config_table: pci_integrator_config_table,
273 void pci_init_board (void)
276 struct pci_controller *hose = &integrator_hose;
278 /* setting this register will take the V3 out of reset */
280 *(volatile unsigned int *) (INTEGRATOR_SC_PCIENABLE) = 1;
282 /* wait a few usecs to settle the device and the PCI bus */
284 for (i = 0; i < 100; i++)
287 /* Now write the Base I/O Address Word to V3_BASE + 0x6C */
289 *(volatile unsigned short *) (V3_BASE + V3_LB_IO_BASE) =
290 (unsigned short) (V3_BASE >> 16);
293 *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) = 0xAA;
294 *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 4) =
296 } while (*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) != 0xAA
297 || *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA +
300 /* Make sure that V3 register access is not locked, if it is, unlock it */
302 if ((*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &
305 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 0xA05F;
307 /* Ensure that the slave accesses from PCI are disabled while we */
310 *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) &=
311 ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
313 /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
315 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &=
316 ~V3_SYSTEM_M_RST_OUT;
318 /* Make all accesses from PCI space retry until we're ready for them */
320 *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) |=
321 V3_PCI_CFG_M_RETRY_EN;
323 /* Set up any V3 PCI Configuration Registers that we absolutely have to */
324 /* LB_CFG controls Local Bus protocol. */
325 /* Enable LocalBus byte strobes for READ accesses too. */
326 /* set bit 7 BE_IMODE and bit 6 BE_OMODE */
328 *(volatile unsigned short *) (V3_BASE + V3_LB_CFG) |= 0x0C0;
330 /* PCI_CMD controls overall PCI operation. */
331 /* Enable PCI bus master. */
333 *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) |= 0x04;
335 /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus */
337 *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP0) =
338 (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512M |
339 V3_PCI_MAP_M_REG_EN |
340 V3_PCI_MAP_M_ENABLE);
342 /* PCI_BASE0 is the PCI address of the start of the window */
344 *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE0) =
345 INTEGRATOR_BOOT_ROM_BASE;
347 /* PCI_MAP1 is LOCAL address of the start of the window */
349 *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP1) =
350 (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1024M |
351 V3_PCI_MAP_M_REG_EN |
352 V3_PCI_MAP_M_ENABLE);
354 /* PCI_BASE1 is the PCI address of the start of the window */
356 *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE1) =
357 INTEGRATOR_HDR0_SDRAM_BASE;
359 /* Set up the windows from local bus memory into PCI configuration, */
360 /* I/O and Memory. */
361 /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */
363 *(volatile unsigned short *) (V3_BASE + V3_LB_BASE2) =
364 ((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
365 *(volatile unsigned short *) (V3_BASE + V3_LB_MAP2) = 0;
367 /* PCI Configuration, use LB_BASE1/LB_MAP1. */
369 /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */
370 /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */
371 /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */
373 *(volatile unsigned int *) (V3_BASE + V3_LB_BASE0) =
374 INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);
376 *(volatile unsigned short *) (V3_BASE + V3_LB_MAP0) =
377 ((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;
379 /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
381 *(volatile unsigned int *) (V3_BASE + V3_LB_BASE1) =
382 INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);
384 *(volatile unsigned short *) (V3_BASE + V3_LB_MAP1) =
385 (((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006;
387 /* Allow accesses to PCI Configuration space */
388 /* and set up A1, A0 for type 1 config cycles */
390 *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) =
391 ((*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG)) &
392 ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1)) |
393 V3_PCI_CFG_M_AD_LOW0;
395 /* now we can allow in PCI MEMORY accesses */
397 *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) =
398 (*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD)) |
401 /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */
402 /* initialise and lock the V3 system register so that no one else */
403 /* can play with it */
405 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
406 (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
409 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
410 (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
416 hose->first_busno = 0;
417 hose->last_busno = 0xff;
419 /* System memory space */
420 pci_set_region (hose->regions + 0,
421 0x00000000, 0x40000000, 0x01000000,
422 PCI_REGION_MEM | PCI_REGION_MEMORY);
424 /* PCI Memory - config space */
425 pci_set_region (hose->regions + 1,
426 0x00000000, 0x62000000, 0x01000000, PCI_REGION_MEM);
429 pci_set_region (hose->regions + 2,
430 0x00000000, 0x61000000, 0x00080000, PCI_REGION_MEM);
433 pci_set_region (hose->regions + 3,
434 0x00000000, 0x60000000, 0x00010000, PCI_REGION_IO);
437 pci_integrator_read_byte,
438 pci_integrator_read__word,
439 pci_integrator_read_dword,
440 pci_integrator_write_byte,
441 pci_integrator_write_word, pci_integrator_write_dword);
443 hose->region_count = 4;
445 pci_register_hose (hose);
447 pciauto_config_init (hose);
448 pciauto_config_device (hose, 0);
450 hose->last_busno = pci_hose_scan (hose);
454 /******************************
457 ******************************/
458 void flash__init (void)
461 /*************************************************************
463 Description: take the Ethernet controller out of reset and wait
464 for the EEPROM load to complete.
465 *************************************************************/
466 void ether__init (void)
470 /******************************
473 ******************************/