1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (C) 2013 Imagination Technologies
8 #include <fdt_support.h>
14 #include <pci_gt64120.h>
15 #include <pci_msc01.h>
17 #include <asm/global_data.h>
18 #include <linux/delay.h>
20 #include <asm/addrspace.h>
22 #include <asm/malta.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define MALTA_GT_PATH "/pci0@1be00000"
29 #define MALTA_MSC_PATH "/pci0@1bd00000"
43 static void malta_lcd_puts(const char *str)
46 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
48 /* print up to 8 characters of the string */
49 for (i = 0; i < min((int)strlen(str), 8); i++) {
50 __raw_writel(str[i], reg);
51 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
54 /* fill the rest of the display with spaces */
56 __raw_writel(' ', reg);
57 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
61 static enum core_card malta_core_card(void)
64 const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
66 rev = __raw_readl(reg);
67 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
70 case MALTA_REVISION_CORID_CORE_LV:
73 case MALTA_REVISION_CORID_CORE_FPGA6:
81 static enum sys_con malta_sys_con(void)
83 switch (malta_core_card()) {
85 return SYSCON_GT64120;
91 return SYSCON_UNKNOWN;
97 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
106 malta_lcd_puts("U-Boot");
107 puts("Board: MIPS Malta");
109 core = malta_core_card();
120 puts(" CoreUnknown");
127 #if !IS_ENABLED(CONFIG_DM_ETH)
128 int board_eth_init(struct bd_info *bis)
130 return pci_eth_init(bis);
134 void _machine_restart(void)
136 void __iomem *reset_base;
138 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
139 __raw_writel(GORESET, reset_base);
143 int board_early_init_f(void)
147 /* choose correct PCI I/O base */
148 switch (malta_sys_con()) {
150 io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
154 io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
161 set_io_port_base(io_base);
163 /* setup FDC37M817 super I/O controller */
164 malta_superio_init();
169 int misc_init_r(void)
176 #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
178 * TODO: currently doesn't work because rw_fdt_blob points to a
179 * NOR flash address. This needs some changes in board_init_f.
181 int board_fix_fdt(void *rw_fdt_blob)
185 switch (malta_sys_con()) {
187 node = fdt_path_offset(rw_fdt_blob, MALTA_GT_PATH);
191 node = fdt_path_offset(rw_fdt_blob, MALTA_MSC_PATH);
195 return fdt_status_okay(rw_fdt_blob, node);
199 int board_early_init_r(void)
206 ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
207 PCI_DEVICE_ID_INTEL_82371AB_0, 0, &dev);
209 panic("Failed to find PIIX4 PCI bridge\n");
211 /* setup PCI interrupt routing */
212 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCA, 10);
213 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCB, 10);
214 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCC, 11);
215 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCD, 11);
217 /* mux SERIRQ onto SERIRQ pin */
218 dm_pci_clrset_config32(dev, PCI_CFG_PIIX4_GENCFG, 0,
219 PCI_CFG_PIIX4_GENCFG_SERIRQ);
221 /* enable SERIRQ - Linux currently depends upon this */
222 dm_pci_clrset_config8(dev, PCI_CFG_PIIX4_SERIRQC, 0,
223 PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT);
225 ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
226 PCI_DEVICE_ID_INTEL_82371AB, 0, &dev);
228 panic("Failed to find PIIX4 IDE controller\n");
230 /* enable bus master & IO access */
231 dm_pci_clrset_config32(dev, PCI_COMMAND, 0,
232 PCI_COMMAND_MASTER | PCI_COMMAND_IO);
235 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
238 dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_PRI,
239 PCI_CFG_PIIX4_IDETIM_IDE);
240 dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_SEC,
241 PCI_CFG_PIIX4_IDETIM_IDE);