2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009 Dave Srl www.dave.eu
4 * (C) Copyright 2010 ifm ecomatic GmbH
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
16 #include <asm/bitops.h>
19 #include <asm/processor.h>
20 #include <asm/mpc512x.h>
21 #include <fdt_support.h>
22 #ifdef CONFIG_MISC_INIT_R
26 static int eeprom_diag;
30 DECLARE_GLOBAL_DATA_PTR;
32 static void gpio_configure(void)
37 im = (immap_t *) CONFIG_SYS_IMMR;
39 out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
40 out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
43 * out_be32(&gpioregs->gpdir, 0xC2293020);
44 * workaround for a hardware effect: configure direction in pieces,
45 * setting all outputs at once drops the reset line too low and
46 * makes us lose the MII connection (breaks ethernet for us)
48 out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
49 setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
51 setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
53 setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
55 setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
57 /* to turn from red to yellow when U-Boot runs */
58 setbits_be32(&gpioregs->gpdat, 0x00002020);
59 out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
60 out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
61 out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
62 out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
65 /* the physical location of the pins */
66 #define GPIOKEY_ROW_BITMASK 0x40000000
67 #define GPIOKEY_ROW_UPPER 0
68 #define GPIOKEY_ROW_LOWER 1
70 #define GPIOKEY_COL0_BITMASK 0x20000000
71 #define GPIOKEY_COL1_BITMASK 0x10000000
72 #define GPIOKEY_COL2_BITMASK 0x08000000
74 /* the logical presentation of pressed keys */
75 #define GPIOKEY_BIT_FNLEFT (1 << 5)
76 #define GPIOKEY_BIT_FNRIGHT (1 << 4)
77 #define GPIOKEY_BIT_DIRUP (1 << 3)
78 #define GPIOKEY_BIT_DIRLEFT (1 << 2)
79 #define GPIOKEY_BIT_DIRRIGHT (1 << 1)
80 #define GPIOKEY_BIT_DIRDOWN (1 << 0)
82 /* the hotkey combination which starts recovery */
83 #define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
86 static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
90 setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
92 clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
96 static u32 gpio_querykbd(void)
103 im = (immap_t *)CONFIG_SYS_IMMR;
104 gpioregs = &im->gpio;
107 /* query upper row */
108 gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
109 input = in_be32(&gpioregs->gpdat);
110 if ((input & GPIOKEY_COL0_BITMASK) == 0)
111 keybits |= GPIOKEY_BIT_FNLEFT;
112 if ((input & GPIOKEY_COL1_BITMASK) == 0)
113 keybits |= GPIOKEY_BIT_DIRUP;
114 if ((input & GPIOKEY_COL2_BITMASK) == 0)
115 keybits |= GPIOKEY_BIT_FNRIGHT;
117 /* query lower row */
118 gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
119 input = in_be32(&gpioregs->gpdat);
120 if ((input & GPIOKEY_COL0_BITMASK) == 0)
121 keybits |= GPIOKEY_BIT_DIRLEFT;
122 if ((input & GPIOKEY_COL1_BITMASK) == 0)
123 keybits |= GPIOKEY_BIT_DIRRIGHT;
124 if ((input & GPIOKEY_COL2_BITMASK) == 0)
125 keybits |= GPIOKEY_BIT_DIRDOWN;
127 /* return bit pattern for keys */
131 /* excerpt from the recovery's hw_info.h */
133 struct __attribute__ ((__packed__)) eeprom_layout {
134 char magic[3]; /** 'ifm' */
135 u8 len[2]; /** content length without magic/len fields */
136 u8 version[3]; /** structure version */
137 u8 type; /** type of PCB */
138 u8 reserved[0x37]; /** padding up to offset 0x40 */
139 u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */
142 #define HW_COMP_MAINCPU 2
144 static struct eeprom_layout eeprom_content;
145 static int eeprom_was_read; /* has_been_read */
146 static int eeprom_is_valid;
147 static int eeprom_version;
149 #define get_eeprom_field_int(name) ({ \
153 for (idx = 0; idx < sizeof(name); idx++) { \
155 value |= name[idx]; \
160 static int read_eeprom(void)
169 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
170 CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
171 (uchar *)&eeprom_content, sizeof(eeprom_content));
173 printf("DIAG: %s() read rc[%d], size[%d]\n",
174 __func__, ret, sizeof(eeprom_content));
183 * check validity of EEPROM content
184 * (check version, length, optionally checksum)
187 eeprom_datalen = get_eeprom_field_int(eeprom_content.len);
188 eeprom_version = get_eeprom_field_int(eeprom_content.version);
191 printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n",
192 __func__, eeprom_content.magic[0],
193 eeprom_content.magic[1], eeprom_content.magic[2],
194 eeprom_datalen, eeprom_version, eeprom_content.type);
196 if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0)
198 if (eeprom_datalen < sizeof(struct eeprom_layout) - 5)
200 if ((eeprom_version != 1) && (eeprom_version != 2))
202 if (eeprom_content.type != HW_COMP_MAINCPU)
206 printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid);
211 int mac_read_from_eeprom(void)
217 printf("I2C EEPROM read failed.\n");
221 if (!eeprom_is_valid) {
222 printf("I2C EEPROM content not valid\n");
227 switch (eeprom_version) {
230 mac = (const u8 *)&eeprom_content.macaddress;
234 if (mac && is_valid_ether_addr(mac)) {
235 eth_setenv_enetaddr("ethaddr", mac);
237 mac_txt = getenv("ethaddr");
239 printf("DIAG: MAC value [%s]\n", mac_txt);
241 printf("DIAG: failed to setup MAC env\n");
250 * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
251 * which the ADS, Aria or PDM360NG boards are using
252 * (the steps outlined here refer to the Micron datasheet)
254 u32 sdram_init_seq[] = {
255 /* item 6, at least one NOP after CKE went high */
256 CONFIG_SYS_DDRCMD_NOP,
257 CONFIG_SYS_DDRCMD_NOP,
258 CONFIG_SYS_DDRCMD_NOP,
259 CONFIG_SYS_DDRCMD_NOP,
260 CONFIG_SYS_DDRCMD_NOP,
261 CONFIG_SYS_DDRCMD_NOP,
262 CONFIG_SYS_DDRCMD_NOP,
263 CONFIG_SYS_DDRCMD_NOP,
264 CONFIG_SYS_DDRCMD_NOP,
265 CONFIG_SYS_DDRCMD_NOP,
266 /* item 7, precharge all; item 8, tRP (20ns) */
267 CONFIG_SYS_DDRCMD_PCHG_ALL,
268 CONFIG_SYS_DDRCMD_NOP,
269 /* item 9, extended mode register; item 10, tMRD 10ns) */
270 CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
271 CONFIG_SYS_DDRCMD_NOP,
273 * item 11, (base) mode register _with_ reset DLL;
274 * item 12, tMRD (10ns)
276 CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
277 CONFIG_SYS_MICRON_BMODE_PARAM,
278 CONFIG_SYS_DDRCMD_NOP,
279 /* item 13, precharge all; item 14, tRP (20ns) */
280 CONFIG_SYS_DDRCMD_PCHG_ALL,
281 CONFIG_SYS_DDRCMD_NOP,
283 * item 15, auto refresh (i.e. refresh with CKE held high);
284 * item 16, tRFC (70ns)
286 CONFIG_SYS_DDRCMD_RFSH,
287 CONFIG_SYS_DDRCMD_NOP,
288 CONFIG_SYS_DDRCMD_NOP,
289 CONFIG_SYS_DDRCMD_NOP,
290 CONFIG_SYS_DDRCMD_NOP,
291 CONFIG_SYS_DDRCMD_NOP,
292 CONFIG_SYS_DDRCMD_NOP,
293 CONFIG_SYS_DDRCMD_NOP,
294 CONFIG_SYS_DDRCMD_NOP,
296 * item 17, auto refresh (i.e. refresh with CKE held high);
297 * item 18, tRFC (70ns)
299 CONFIG_SYS_DDRCMD_RFSH,
300 CONFIG_SYS_DDRCMD_NOP,
301 CONFIG_SYS_DDRCMD_NOP,
302 CONFIG_SYS_DDRCMD_NOP,
303 CONFIG_SYS_DDRCMD_NOP,
304 CONFIG_SYS_DDRCMD_NOP,
305 CONFIG_SYS_DDRCMD_NOP,
306 CONFIG_SYS_DDRCMD_NOP,
307 CONFIG_SYS_DDRCMD_NOP,
308 /* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
309 CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
310 CONFIG_SYS_DDRCMD_NOP,
312 * item 21, "actually done", but make sure 200 DRAM clock cycles
313 * have passed after DLL reset before READ requests are issued
314 * (200 cycles at 160MHz -> 1.25 usec)
316 /* EMPTY, optional, we don't do it */
319 phys_size_t initdram(int board_type)
321 return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
324 int misc_init_r(void)
330 /* we use bus I2C-0 for the on-board eeprom */
333 /* setup GPIO directions and initial values */
337 * enforce the start of the recovery system when
338 * - the appropriate keys were pressed
339 * - "some" external software told us to
340 * - a previous installation was aborted or has failed
343 keys = gpio_querykbd();
345 printf("GPIO keyboard status [0x%02X]\n", keys);
346 if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
347 printf("detected recovery request (keyboard)\n");
350 s = getenv("want_recovery");
351 if ((s != NULL) && (*s != '\0')) {
352 printf("detected recovery request (environment)\n");
355 s = getenv("install_in_progress");
356 if ((s != NULL) && (*s != '\0')) {
357 printf("previous installation has not completed\n");
360 s = getenv("install_failed");
361 if ((s != NULL) && (*s != '\0')) {
362 printf("previous installation has failed\n");
366 printf("enforced start of the recovery system\n");
367 setenv("bootcmd", "run recovery");
371 * boot the recovery system without waiting; boot the
372 * production system without waiting by default, only
373 * insert a pause (to provide a chance to get a prompt)
374 * when GPIO keys were pressed during power on
377 setenv("bootdelay", "0");
379 setenv("bootdelay", "0");
381 setenv("bootdelay", "2");
383 /* get the ethernet MAC from I2C EEPROM */
384 mac_read_from_eeprom();
389 /* setup specific IO pad configuration */
390 static iopin_t ioregs_init[] = {
392 offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
393 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
394 IO_PIN_FMUX(1) | IO_PIN_DS(2),
397 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
402 offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
407 offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
408 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
409 IO_PIN_FMUX(1) | IO_PIN_DS(2),
411 { /* SDHC CLK, CMD, D0, D1, D2, D3 */
412 offsetof(struct ioctrl512x, io_control_pata_ior), 6,
413 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
414 IO_PIN_FMUX(1) | IO_PIN_DS(2),
416 { /* GPIO keyboard */
417 offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
421 { /* GPIO DN1 PF, LCD power, DN2 PF */
422 offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
426 { /* GPIO reset AS-i */
427 offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
431 { /* GPIO reset safety */
432 offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
436 { /* GPIO reset netX */
437 offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
442 offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
446 { /* GPIO SD CD, SD WP */
447 offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
452 offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
453 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
454 IO_PIN_FMUX(2) | IO_PIN_DS(2),
456 { /* GPIO AS-i prog, AS-i done, LCD backlight */
457 offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
461 { /* GPIO AS-i wdg */
462 offsetof(struct ioctrl512x, io_control_pci_req2), 1,
466 { /* GPIO safety wdg */
467 offsetof(struct ioctrl512x, io_control_pci_req1), 1,
471 { /* GPIO netX wdg */
472 offsetof(struct ioctrl512x, io_control_pci_req0), 1,
476 { /* GPIO IRQ powerfail */
477 offsetof(struct ioctrl512x, io_control_pci_inta), 1,
481 { /* GPIO AS-i PWRD */
482 offsetof(struct ioctrl512x, io_control_pci_frame), 1,
486 { /* GPIO LED0, LED1 */
487 offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
491 { /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
492 offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
497 offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
498 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
499 IO_PIN_FMUX(2) | IO_PIN_DS(2),
501 { /* FEC TX ER, CRS */
502 offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
503 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
504 IO_PIN_FMUX(1) | IO_PIN_DS(2),
506 { /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
507 offsetof(struct ioctrl512x, io_control_irq0), 1,
512 * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
513 * rdx 3-0, mdio, rx clk
515 offsetof(struct ioctrl512x, io_control_psc0_0), 15,
516 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
517 IO_PIN_FMUX(1) | IO_PIN_DS(2),
519 /* optional: make sure PSC3 remains the serial console */
521 offsetof(struct ioctrl512x, io_control_psc3_4), 1,
522 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
523 IO_PIN_FMUX(1) | IO_PIN_DS(2),
525 /* make sure PSC4 remains available for SPI,
526 *BUT* PSC4_1 is a GPIO kind of SS! */
527 { /* enforce drive strength on the SPI pin */
528 offsetof(struct ioctrl512x, io_control_psc4_0), 5,
533 offsetof(struct ioctrl512x, io_control_psc4_1), 1,
537 /* optional: make sure PSC5 remains available for SPI */
538 { /* enforce drive strength on the SPI pin */
539 offsetof(struct ioctrl512x, io_control_psc5_0), 5,
544 offsetof(struct ioctrl512x, io_control_psc6_0), 1,
545 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
546 IO_PIN_FMUX(1) | IO_PIN_DS(2),
549 offsetof(struct ioctrl512x, io_control_psc6_1), 1,
550 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
551 IO_PIN_FMUX(2) | IO_PIN_DS(1),
554 offsetof(struct ioctrl512x, io_control_psc6_4), 1,
555 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
556 IO_PIN_FMUX(2) | IO_PIN_DS(1),
558 { /* PSC7, part of DIU RGB */
559 offsetof(struct ioctrl512x, io_control_psc7_0), 2,
560 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
561 IO_PIN_FMUX(2) | IO_PIN_DS(1),
563 { /* PSC7, safety UART */
564 offsetof(struct ioctrl512x, io_control_psc7_2), 2,
565 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
566 IO_PIN_FMUX(0) | IO_PIN_DS(1),
568 { /* DIU (part of) RGB[] */
569 offsetof(struct ioctrl512x, io_control_psc8_3), 16,
570 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
571 IO_PIN_FMUX(2) | IO_PIN_DS(1),
573 { /* DIU data enable */
574 offsetof(struct ioctrl512x, io_control_psc11_4), 1,
575 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
576 IO_PIN_FMUX(2) | IO_PIN_DS(1),
578 /* reduce LPB drive strength for improved EMI */
579 { /* LPC OE, LPC RW */
580 offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
584 { /* LPC AX03 through LPC AD00 */
585 offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
590 offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
595 offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
600 offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
608 puts("Board: ifm AC14xx\n");
610 /* initialize function mux & slew rate IO inter alia on IO Pins */
611 iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
616 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
617 void ft_board_setup(void *blob, bd_t *bd)
619 ft_cpu_setup(blob, bd);
621 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */