1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2017 Linaro
4 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
11 #include <asm/cache.h>
13 #include <dm/platform_data/serial_pl01x.h>
14 #include <asm/arch/hi3798cv200.h>
15 #include <asm/armv8/mmu.h>
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 static struct mm_region poplar_mem_map[] = {
26 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
32 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
34 PTE_BLOCK_PXN | PTE_BLOCK_UXN
40 struct mm_region *mem_map = poplar_mem_map;
42 #if !CONFIG_IS_ENABLED(OF_CONTROL)
43 static const struct pl01x_serial_plat serial_plat = {
44 .base = REG_BASE_UART0,
49 U_BOOT_DRVINFO(poplar_serial) = {
50 .name = "serial_pl01x",
57 puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
62 void reset_cpu(ulong addr)
69 gd->ram_size = get_ram_size(NULL, 0x80000000);
75 * Some linux kernel versions don't use memory before its load address, so to
76 * be generic we just pretend it isn't there. In previous uboot versions we
77 * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
78 * could persist in memory and be left alone by the kernel.
80 * That led to a problem when mapping memory in older kernels. That PSCI code
81 * now lies in memory below the kernel load offset; it therefore won't be
82 * touched by the kernel, and by not specially reserving it we avoid the mapping
86 #define KERNEL_TEXT_OFFSET 0x00080000
88 int dram_init_banksize(void)
90 gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
91 gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
96 static void usb2_phy_config(void)
98 const u32 config[] = {
99 /* close EOP pre-emphasis. open data pre-emphasis */
101 /* Rcomp = 150mW, increase DC level */
103 /* keep Rcomp working */
105 /* Icomp = 212mW, increase current drive */
107 /* EMI fix: rx_active not stay 1 when error packets received */
109 /* Comp mode select */
111 /* adjust eye diagram */
113 /* adjust eye diagram */
118 for (i = 0; i < ARRAY_SIZE(config); i++) {
119 writel(config[i], PERI_CTRL_USB0);
120 clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22));
125 static void usb2_phy_init(void)
127 /* reset usb2 controller bus/utmi/roothub */
128 setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
129 USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
132 /* reset usb2 phy por/utmi */
133 setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1);
136 /* open usb2 ref clk */
137 setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN);
140 /* cancel usb2 power on reset */
141 clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ);
146 /* cancel usb2 port reset, wait comp circuit stable */
147 clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1);
150 /* open usb2 controller clk */
151 setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN |
152 USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN |
153 USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
156 /* cancel usb2 control reset */
157 clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
158 USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
162 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
165 #include <usb/dwc2_udc.h>
168 static struct dwc2_plat_otg_data poplar_otg_data = {
169 .regs_otg = HIOTG_BASE_ADDR
172 static void set_usb_to_device(void)
174 setbits_le32(PERI_CTRL_USB3, USB2_2P_CHIPID);
177 int board_usb_init(int index, enum usb_init_type init)
180 return dwc2_udc_probe(&poplar_otg_data);
183 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
185 if (!env_get("serial#"))
186 g_dnl_set_serialnumber("0123456789POPLAR");