1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Linaro
4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11 #include <asm/cache.h>
14 #include <asm/arch/hi3660.h>
15 #include <asm/armv8/mmu.h>
17 #include <linux/arm-smccc.h>
18 #include <linux/psci.h>
20 #define PMIC_REG_TO_BUS_ADDR(x) (x << 2)
21 #define PMIC_VSEL_MASK 0x7
23 DECLARE_GLOBAL_DATA_PTR;
25 #if !CONFIG_IS_ENABLED(OF_CONTROL)
26 #include <dm/platform_data/serial_pl01x.h>
28 static const struct pl01x_serial_platdata serial_platdata = {
29 .base = HI3660_UART6_BASE,
34 U_BOOT_DEVICE(hikey960_serial0) = {
35 .name = "serial_pl01x",
36 .platdata = &serial_platdata,
40 static struct mm_region hikey_mem_map[] = {
42 .virt = 0x0UL, /* DDR */
45 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
48 .virt = 0xE0000000UL, /* Peripheral block */
51 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
53 PTE_BLOCK_PXN | PTE_BLOCK_UXN
60 struct mm_region *mem_map = hikey_mem_map;
62 int board_early_init_f(void)
74 gd->ram_size = PHYS_SDRAM_1_SIZE;
79 int dram_init_banksize(void)
81 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
82 gd->bd->bi_dram[0].size = gd->ram_size;
87 void hikey960_sd_init(void)
92 data = readl(SCTRL_SCFPLLCTRL0);
93 data |= SCTRL_SCFPLLCTRL0_FPLL0_EN;
94 writel(data, SCTRL_SCFPLLCTRL0);
97 data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79)) &
100 writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79));
102 data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
104 writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
109 data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b)) &
112 writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b));
114 data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
116 writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
121 writel(0, PINMUX4_SDDET);
124 writel(15 << 4, PINCONF3_SDCLK);
125 writel((1 << 0) | (8 << 4), PINCONF3_SDCMD);
126 writel((1 << 0) | (8 << 4), PINCONF3_SDDATA0);
127 writel((1 << 0) | (8 << 4), PINCONF3_SDDATA1);
128 writel((1 << 0) | (8 << 4), PINCONF3_SDDATA2);
129 writel((1 << 0) | (8 << 4), PINCONF3_SDDATA3);
131 /* Set SD clock mux */
133 data = readl(CRG_REG_BASE + 0xb8);
134 data |= ((1 << 6) | (1 << 6 << 16) | (0 << 4) | (3 << 4 << 16));
135 writel(data, CRG_REG_BASE + 0xb8);
137 data = readl(CRG_REG_BASE + 0xb8);
138 } while ((data & ((1 << 6) | (3 << 4))) != ((1 << 6) | (0 << 4)));
140 /* Take SD out of reset */
141 writel(1 << 18, CRG_PERRSTDIS4);
143 data = readl(CRG_PERRSTSTAT4);
144 } while ((data & (1 << 18)) == (1 << 18));
146 /* Enable hclk_gate_sd */
147 data = readl(CRG_REG_BASE + 0);
149 writel(data, CRG_REG_BASE + 0);
151 /* Enable clk_andgt_mmc */
152 data = readl(CRG_REG_BASE + 0xf4);
153 data |= ((1 << 3) | (1 << 3 << 16));
154 writel(data, CRG_REG_BASE + 0xf4);
156 /* Enable clk_gate_sd */
157 data = readl(CRG_PEREN4);
159 writel(data, CRG_PEREN4);
161 data = readl(CRG_PERCLKEN4);
162 } while ((data & (1 << 17)) != (1 << 17));
165 static void show_psci_version(void)
167 struct arm_smccc_res res;
169 arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
171 printf("PSCI: v%ld.%ld\n",
172 PSCI_VERSION_MAJOR(res.a0),
173 PSCI_VERSION_MINOR(res.a0));
186 void reset_cpu(ulong addr)