1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2015 Linaro
4 * Peter Griffin <peter.griffin@linaro.org>
9 #include <fdt_support.h>
10 #include <dm/platform_data/serial_pl01x.h>
16 #include <power/hi6553_pmic.h>
17 #include <asm-generic/gpio.h>
18 #include <asm/arch/dwmmc.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/periph.h>
21 #include <asm/arch/pinmux.h>
22 #include <asm/arch/hi6220.h>
23 #include <asm/armv8/mmu.h>
25 /*TODO drop this table in favour of device tree */
26 static const struct hikey_gpio_platdata hi6220_gpio[] = {
27 { 0, HI6220_GPIO_BASE(0)},
28 { 1, HI6220_GPIO_BASE(1)},
29 { 2, HI6220_GPIO_BASE(2)},
30 { 3, HI6220_GPIO_BASE(3)},
31 { 4, HI6220_GPIO_BASE(4)},
32 { 5, HI6220_GPIO_BASE(5)},
33 { 6, HI6220_GPIO_BASE(6)},
34 { 7, HI6220_GPIO_BASE(7)},
35 { 8, HI6220_GPIO_BASE(8)},
36 { 9, HI6220_GPIO_BASE(9)},
37 { 10, HI6220_GPIO_BASE(10)},
38 { 11, HI6220_GPIO_BASE(11)},
39 { 12, HI6220_GPIO_BASE(12)},
40 { 13, HI6220_GPIO_BASE(13)},
41 { 14, HI6220_GPIO_BASE(14)},
42 { 15, HI6220_GPIO_BASE(15)},
43 { 16, HI6220_GPIO_BASE(16)},
44 { 17, HI6220_GPIO_BASE(17)},
45 { 18, HI6220_GPIO_BASE(18)},
46 { 19, HI6220_GPIO_BASE(19)},
50 U_BOOT_DEVICES(hi6220_gpios) = {
51 { "gpio_hi6220", &hi6220_gpio[0] },
52 { "gpio_hi6220", &hi6220_gpio[1] },
53 { "gpio_hi6220", &hi6220_gpio[2] },
54 { "gpio_hi6220", &hi6220_gpio[3] },
55 { "gpio_hi6220", &hi6220_gpio[4] },
56 { "gpio_hi6220", &hi6220_gpio[5] },
57 { "gpio_hi6220", &hi6220_gpio[6] },
58 { "gpio_hi6220", &hi6220_gpio[7] },
59 { "gpio_hi6220", &hi6220_gpio[8] },
60 { "gpio_hi6220", &hi6220_gpio[9] },
61 { "gpio_hi6220", &hi6220_gpio[10] },
62 { "gpio_hi6220", &hi6220_gpio[11] },
63 { "gpio_hi6220", &hi6220_gpio[12] },
64 { "gpio_hi6220", &hi6220_gpio[13] },
65 { "gpio_hi6220", &hi6220_gpio[14] },
66 { "gpio_hi6220", &hi6220_gpio[15] },
67 { "gpio_hi6220", &hi6220_gpio[16] },
68 { "gpio_hi6220", &hi6220_gpio[17] },
69 { "gpio_hi6220", &hi6220_gpio[18] },
70 { "gpio_hi6220", &hi6220_gpio[19] },
73 DECLARE_GLOBAL_DATA_PTR;
75 #if !CONFIG_IS_ENABLED(OF_CONTROL)
77 static const struct pl01x_serial_platdata serial_platdata = {
78 #if CONFIG_CONS_INDEX == 1
79 .base = HI6220_UART0_BASE,
80 #elif CONFIG_CONS_INDEX == 4
81 .base = HI6220_UART3_BASE,
83 #error "Unsupported console index value."
89 U_BOOT_DEVICE(hikey_seriala) = {
90 .name = "serial_pl01x",
91 .platdata = &serial_platdata,
95 static struct mm_region hikey_mem_map[] = {
100 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
101 PTE_BLOCK_INNER_SHARE
103 .virt = 0x80000000UL,
104 .phys = 0x80000000UL,
105 .size = 0x80000000UL,
106 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
107 PTE_BLOCK_NON_SHARE |
108 PTE_BLOCK_PXN | PTE_BLOCK_UXN
110 /* List terminator */
115 struct mm_region *mem_map = hikey_mem_map;
117 #ifdef CONFIG_BOARD_EARLY_INIT_F
118 int board_uart_init(void)
120 switch (CONFIG_CONS_INDEX) {
122 hi6220_pinmux_config(PERIPH_ID_UART0);
125 hi6220_pinmux_config(PERIPH_ID_UART3);
128 debug("%s: Unsupported UART selected\n", __func__);
135 int board_early_init_f(void)
142 struct peri_sc_periph_regs *peri_sc =
143 (struct peri_sc_periph_regs *)HI6220_PERI_BASE;
145 struct alwayson_sc_regs *ao_sc =
146 (struct alwayson_sc_regs *)ALWAYSON_CTRL_BASE;
148 /* status offset from enable reg */
149 #define STAT_EN_OFF 0x2
151 void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base)
155 data = readl(clk_base);
158 writel(bitfield, clk_base);
160 data = readl(clk_base + STAT_EN_OFF);
161 } while ((data & bitfield) == 0);
164 /* status offset from disable reg */
165 #define STAT_DIS_OFF 0x1
167 void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base)
171 data = readl(clk_base);
174 writel(data, clk_base);
176 data = readl(clk_base + STAT_DIS_OFF);
177 } while (data & bitfield);
180 #define EYE_PATTERN 0x70533483
182 int board_usb_init(int index, enum usb_init_type init)
186 /* enable USB clock */
187 hi6220_clk_enable(PERI_CLK0_USBOTG, &peri_sc->clk0_en);
189 /* take usb IPs out of reset */
190 writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
191 PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,
194 data = readl(&peri_sc->rst0_stat);
195 data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
196 PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;
200 data = readl(&peri_sc->ctrl5);
201 data &= ~PERI_CTRL5_PICOPHY_BC_MODE;
202 data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;
204 writel(data, &peri_sc->ctrl5);
208 /* configure USB PHY */
209 data = readl(&peri_sc->ctrl4);
211 /* make PHY out of low power mode */
212 data &= ~PERI_CTRL4_PICO_SIDDQ;
213 data &= ~PERI_CTRL4_PICO_OGDISABLE;
214 data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;
215 writel(data, &peri_sc->ctrl4);
217 writel(EYE_PATTERN, &peri_sc->ctrl8);
223 static int config_sd_carddetect(void)
227 /* configure GPIO8 as nopull */
228 writel(0, 0xf8001830);
230 gpio_request(8, "SD CD");
232 gpio_direction_input(8);
233 ret = gpio_get_value(8);
236 printf("%s: SD card present\n", __func__);
240 printf("%s: SD card not present\n", __func__);
245 static void mmc1_init_pll(void)
249 /* select SYSPLL as the source of MMC1 */
250 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
251 writel(1 << 11 | 1 << 27, &peri_sc->clk0_sel);
253 data = readl(&peri_sc->clk0_sel);
254 } while (!(data & (1 << 11)));
256 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
257 writel(1 << 30, &peri_sc->clk0_sel);
259 data = readl(&peri_sc->clk0_sel);
260 } while (data & (1 << 14));
262 hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
264 hi6220_clk_enable(PERI_CLK12_MMC1_SRC, &peri_sc->clk12_en);
267 /* 1.2GHz / 50 = 24MHz */
268 writel(0x31 | (1 << 7), &peri_sc->clkcfg8bit2);
269 data = readl(&peri_sc->clkcfg8bit2);
270 } while ((data & 0x31) != 0x31);
273 static void mmc1_reset_clk(void)
277 /* disable mmc1 bus clock */
278 hi6220_clk_disable(PERI_CLK0_MMC1, &peri_sc->clk0_dis);
280 /* enable mmc1 bus clock */
281 hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
283 /* reset mmc1 clock domain */
284 writel(PERI_RST0_MMC1, &peri_sc->rst0_en);
286 /* bypass mmc1 clock phase */
287 data = readl(&peri_sc->ctrl2);
289 writel(data, &peri_sc->ctrl2);
291 /* disable low power */
292 data = readl(&peri_sc->ctrl13);
294 writel(data, &peri_sc->ctrl13);
296 data = readl(&peri_sc->rst0_stat);
297 } while (!(data & PERI_RST0_MMC1));
299 /* unreset mmc1 clock domain */
300 writel(PERI_RST0_MMC1, &peri_sc->rst0_dis);
302 data = readl(&peri_sc->rst0_stat);
303 } while (data & PERI_RST0_MMC1);
306 static void mmc0_reset_clk(void)
310 /* disable mmc0 bus clock */
311 hi6220_clk_disable(PERI_CLK0_MMC0, &peri_sc->clk0_dis);
313 /* enable mmc0 bus clock */
314 hi6220_clk_enable(PERI_CLK0_MMC0, &peri_sc->clk0_en);
316 /* reset mmc0 clock domain */
317 writel(PERI_RST0_MMC0, &peri_sc->rst0_en);
319 /* bypass mmc0 clock phase */
320 data = readl(&peri_sc->ctrl2);
322 writel(data, &peri_sc->ctrl2);
324 /* disable low power */
325 data = readl(&peri_sc->ctrl13);
327 writel(data, &peri_sc->ctrl13);
329 data = readl(&peri_sc->rst0_stat);
330 } while (!(data & PERI_RST0_MMC0));
332 /* unreset mmc0 clock domain */
333 writel(PERI_RST0_MMC0, &peri_sc->rst0_dis);
335 data = readl(&peri_sc->rst0_stat);
336 } while (data & PERI_RST0_MMC0);
340 /* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
341 static void hi6220_pmussi_init(void)
345 /* Take PMUSSI out of reset */
346 writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,
349 data = readl(&ao_sc->rst4_stat);
350 } while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);
352 /* set PMU SSI clock latency for read operation */
353 data = readl(&ao_sc->mcu_subsys_ctrl3);
354 data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
355 data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;
356 writel(data, &ao_sc->mcu_subsys_ctrl3);
358 /* enable PMUSSI clock */
359 data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |
360 ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;
362 hi6220_clk_enable(data, &ao_sc->clk5_en);
364 /* Output high to PMIC on PWR_HOLD_GPIO0_0 */
365 gpio_request(0, "PWR_HOLD_GPIO0_0");
366 gpio_direction_output(0, 1);
369 int misc_init_r(void)
381 static int init_dwmmc(void)
387 /* mmc0 pll is already configured by ATF */
389 ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
391 printf("%s: Error configuring pinmux for eMMC (%d)\n"
394 ret |= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);
396 printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
399 /* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
403 ret |= hi6220_pinmux_config(PERIPH_ID_SDMMC1);
405 printf("%s: Error configuring pinmux for eMMC (%d)\n"
408 config_sd_carddetect();
410 ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);
412 printf("%s: Error adding SD port (%d)\n", __func__, ret);
418 /* setup board specific PMIC */
419 int power_init_board(void)
421 /* init the hi6220 pmussi ip */
422 hi6220_pmussi_init();
424 power_hi6553_init((u8 *)HI6220_PMUSSI_BASE);
429 int board_mmc_init(bd_t *bis)
433 /* add the eMMC and sd ports */
437 debug("init_dwmmc failed\n");
445 gd->ram_size = PHYS_SDRAM_1_SIZE;
449 int dram_init_banksize(void)
452 * Reserve regions below from DT memory node (which gets generated
453 * by U-Boot from the dram banks in arch_fixup_fdt() before booting
454 * the kernel. This will then match the kernel hikey dts memory node.
456 * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
457 * 0x05f0,1000 - 0x05f0,1fff: Reboot reason
458 * 0x06df,f000 - 0x06df,ffff: Mailbox message data
459 * 0x0740,f000 - 0x0740,ffff: MCU firmware section
460 * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
461 * 0x3e00,0000 - 0x3fff,ffff: OP-TEE
464 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
465 gd->bd->bi_dram[0].size = 0x05e00000;
467 gd->bd->bi_dram[1].start = 0x05f00000;
468 gd->bd->bi_dram[1].size = 0x00001000;
470 gd->bd->bi_dram[2].start = 0x05f02000;
471 gd->bd->bi_dram[2].size = 0x00efd000;
473 gd->bd->bi_dram[3].start = 0x06e00000;
474 gd->bd->bi_dram[3].size = 0x0060f000;
476 gd->bd->bi_dram[4].start = 0x07410000;
477 gd->bd->bi_dram[4].size = 0x1aaf0000;
479 gd->bd->bi_dram[5].start = 0x22000000;
480 gd->bd->bi_dram[5].size = 0x1c000000;
485 void reset_cpu(ulong addr)
487 writel(0x48698284, &ao_sc->stat0);