board/gumstix/pepper/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for Gumstix Pepper and AM335x-based boards
   4  *
   5  * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
   6  * Based on board/ti/am335x/board.c from Texas Instruments, Inc.
   7  */
   8
   9 #include <common.h>
  10 #include <env.h>
  11 #include <errno.h>
  12 #include <net.h>
  13 #include <serial.h>
  14 #include <spl.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/omap.h>
  18 #include <asm/arch/ddr_defs.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/mmc_host_def.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mem.h>
  24 #include <asm/io.h>
  25 #include <asm/emif.h>
  26 #include <asm/gpio.h>
  27 #include <i2c.h>
  28 #include <miiphy.h>
  29 #include <cpsw.h>
  30 #include <power/tps65217.h>
  31 #include <watchdog.h>
  32 #include "board.h"
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #ifdef CONFIG_SPL_BUILD
  37 #define OSC     (V_OSCK/1000000)
  38
  39 static const struct ddr_data ddr3_data = {
  40         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  41         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  42         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  43         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  44 };
  45
  46 static const struct cmd_control ddr3_cmd_ctrl_data = {
  47         .cmd0csratio = MT41K256M16HA125E_RATIO,
  48         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  49
  50         .cmd1csratio = MT41K256M16HA125E_RATIO,
  51         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  52
  53         .cmd2csratio = MT41K256M16HA125E_RATIO,
  54         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  55 };
  56
  57 static struct emif_regs ddr3_emif_reg_data = {
  58         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  59         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  60         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  61         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  62         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  63         .zq_config = MT41K256M16HA125E_ZQ_CFG,
  64         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  65 };
  66
  67 const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1};
  68
  69 const struct ctrl_ioregs ioregs_ddr3 = {
  70         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  71         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  72         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  73         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  74         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  75 };
  76
  77 static const struct ddr_data ddr2_data = {
  78         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  79         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  80         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  81 };
  82
  83 static const struct cmd_control ddr2_cmd_ctrl_data = {
  84         .cmd0csratio = MT47H128M16RT25E_RATIO,
  85
  86         .cmd1csratio = MT47H128M16RT25E_RATIO,
  87
  88         .cmd2csratio = MT47H128M16RT25E_RATIO,
  89 };
  90
  91 static const struct emif_regs ddr2_emif_reg_data = {
  92         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  93         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  94         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  95         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  96         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  97         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  98 };
  99
 100 const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1};
 101
 102 const struct ctrl_ioregs ioregs_ddr2 = {
 103         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 104         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 105         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 106         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 107         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 108 };
 109
 110 static int read_eeprom(struct pepper_board_id *header)
 111 {
 112         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
 113                 return -ENODEV;
 114         }
 115
 116         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
 117                 sizeof(struct pepper_board_id))) {
 118                 return -EIO;
 119         }
 120
 121         return 0;
 122 }
 123
 124 const struct dpll_params *get_dpll_ddr_params(void)
 125 {
 126         struct pepper_board_id header;
 127
 128         enable_i2c0_pin_mux();
 129         i2c_set_bus_num(0);
 130
 131         if (read_eeprom(&header) < 0)
 132                 return &dpll_ddr3;
 133
 134         switch (header.device_vendor) {
 135         case GUMSTIX_PEPPER:
 136                 return &dpll_ddr2;
 137         case GUMSTIX_PEPPER_DVI:
 138                 return &dpll_ddr3;
 139         default:
 140                 return &dpll_ddr3;
 141         }
 142 }
 143
 144 void sdram_init(void)
 145 {
 146         const struct dpll_params *dpll = get_dpll_ddr_params();
 147
 148         /*
 149          * Here we are assuming PLL clock reveals the type of RAM.
 150          * DDR2 = 266
 151          * DDR3 = 400
 152          * Note that DDR3 is the default.
 153          */
 154         if (dpll->m == 266) {
 155                 config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data,
 156                         &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 157         }
 158         else if (dpll->m == 400) {
 159                 config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data,
 160                         &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 161         }
 162 }
 163
 164 #ifdef CONFIG_SPL_OS_BOOT
 165 int spl_start_uboot(void)
 166 {
 167         /* break into full u-boot on 'c' */
 168         return serial_tstc() && serial_getc() == 'c';
 169 }
 170 #endif
 171
 172 void set_uart_mux_conf(void)
 173 {
 174         enable_uart0_pin_mux();
 175 }
 176
 177 void set_mux_conf_regs(void)
 178 {
 179         enable_board_pin_mux();
 180 }
 181
 182
 183 #endif
 184
 185 int board_init(void)
 186 {
 187 #if defined(CONFIG_HW_WATCHDOG)
 188         hw_watchdog_init();
 189 #endif
 190
 191         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 192         gpmc_init();
 193
 194         return 0;
 195 }
 196
 197 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 198         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 199 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 200
 201 static void cpsw_control(int enabled)
 202 {
 203         /* VTP can be added here */
 204
 205         return;
 206 }
 207
 208 static struct cpsw_slave_data cpsw_slaves[] = {
 209         {
 210                 .slave_reg_ofs  = 0x208,
 211                 .sliver_reg_ofs = 0xd80,
 212                 .phy_addr       = 0,
 213                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
 214         },
 215 };
 216
 217 static struct cpsw_platform_data cpsw_data = {
 218         .mdio_base              = CPSW_MDIO_BASE,
 219         .cpsw_base              = CPSW_BASE,
 220         .mdio_div               = 0xff,
 221         .channels               = 8,
 222         .cpdma_reg_ofs          = 0x800,
 223         .slaves                 = 1,
 224         .slave_data             = cpsw_slaves,
 225         .ale_reg_ofs            = 0xd00,
 226         .ale_entries            = 1024,
 227         .host_port_reg_ofs      = 0x108,
 228         .hw_stats_reg_ofs       = 0x900,
 229         .bd_ram_ofs             = 0x2000,
 230         .mac_control            = (1 << 5),
 231         .control                = cpsw_control,
 232         .host_port_num          = 0,
 233         .version                = CPSW_CTRL_VERSION_2,
 234 };
 235
 236 int board_eth_init(bd_t *bis)
 237 {
 238         int rv, n = 0;
 239         uint8_t mac_addr[6];
 240         uint32_t mac_hi, mac_lo;
 241         const char *devname;
 242
 243         if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 244                 /* try reading mac address from efuse */
 245                 mac_lo = readl(&cdev->macid0l);
 246                 mac_hi = readl(&cdev->macid0h);
 247                 mac_addr[0] = mac_hi & 0xFF;
 248                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 249                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 250                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 251                 mac_addr[4] = mac_lo & 0xFF;
 252                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 253                 if (is_valid_ethaddr(mac_addr))
 254                         eth_env_set_enetaddr("ethaddr", mac_addr);
 255         }
 256
 257         writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 258
 259         rv = cpsw_register(&cpsw_data);
 260         if (rv < 0)
 261                 printf("Error %d registering CPSW switch\n", rv);
 262         else
 263                 n += rv;
 264
 265         /*
 266          *
 267          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 268          * operating points.  So we must set the TX clock delay feature
 269          * in the KSZ9021 PHY.  Since we only support a single ethernet
 270          * device in U-Boot, we only do this for the current instance.
 271          */
 272         devname = miiphy_get_current_dev();
 273         /* max rx/tx clock delay, min rx/tx control delay */
 274         miiphy_write(devname, 0x0, 0x0b, 0x8104);
 275         miiphy_write(devname, 0x0, 0xc, 0xa0a0);
 276
 277         /* min rx data delay */
 278         miiphy_write(devname, 0x0, 0x0b, 0x8105);
 279         miiphy_write(devname, 0x0, 0x0c, 0x0000);
 280
 281         /* min tx data delay */
 282         miiphy_write(devname, 0x0, 0x0b, 0x8106);
 283         miiphy_write(devname, 0x0, 0x0c, 0x0000);
 284
 285         return n;
 286 }
 287 #endif