1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright (C) 2016 Grinn
10 #include <asm/arch/clock.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/litesom.h>
15 #include <asm/arch/mx6ul_pins.h>
16 #include <asm/arch/mx6-pins.h>
17 #include <asm/arch/sys_proto.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/mach-imx/boot_mode.h>
24 #include <fsl_esdhc_imx.h>
25 #include <linux/sizes.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
40 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
43 PAD_CTL_SPEED_HIGH | \
44 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
46 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
47 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
49 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
51 static iomux_v3_cfg_t const uart1_pads[] = {
52 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
53 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
56 static iomux_v3_cfg_t const sd_pads[] = {
57 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
60 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
61 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
62 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
65 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
68 static void setup_iomux_uart(void)
70 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
73 #ifdef CONFIG_FSL_ESDHC_IMX
74 static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};
76 #define SD_CD_GPIO IMX_GPIO_NR(1, 19)
78 static int mmc_get_env_devno(void)
80 u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
84 bootsel = (soc_sbmr & 0x000000FF) >> 6;
86 /* If not boot from sd/mmc, use default value */
88 return CONFIG_SYS_MMC_ENV_DEV;
90 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
91 dev_no = (soc_sbmr & 0x00001800) >> 11;
96 int board_mmc_getcd(struct mmc *mmc)
98 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
101 switch (cfg->esdhc_base) {
102 case USDHC1_BASE_ADDR:
103 ret = !gpio_get_value(SD_CD_GPIO);
105 case USDHC2_BASE_ADDR:
113 int board_mmc_init(struct bd_info *bis)
118 imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads));
119 gpio_direction_input(SD_CD_GPIO);
120 sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
122 ret = fsl_esdhc_initialize(bis, &sd_cfg);
124 printf("Warning: failed to initialize mmc dev 0 (SD)\n");
128 return litesom_mmc_init(bis);
131 static int check_mmc_autodetect(void)
133 char *autodetect_str = env_get("mmcautodetect");
135 if ((autodetect_str != NULL) &&
136 (strcmp(autodetect_str, "yes") == 0)) {
143 void board_late_mmc_init(void)
147 u32 dev_no = mmc_get_env_devno();
149 if (!check_mmc_autodetect())
152 env_set_ulong("mmcdev", dev_no);
155 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
157 env_set("mmcroot", mmcblk);
159 sprintf(cmd, "mmc dev %d", dev_no);
164 #ifdef CONFIG_FEC_MXC
165 static int setup_fec(void)
167 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
170 /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13],
172 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
173 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
175 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
185 int board_early_init_f(void)
194 /* Address of boot parameters */
195 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
197 #ifdef CONFIG_FEC_MXC
204 #ifdef CONFIG_CMD_BMODE
205 static const struct boot_mode board_boot_modes[] = {
206 /* 4 bit bus width */
207 {"sd", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
208 {"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)},
213 int board_late_init(void)
215 #ifdef CONFIG_CMD_BMODE
216 add_board_boot_modes(board_boot_modes);
219 #ifdef CONFIG_ENV_IS_IN_MMC
220 board_late_mmc_init();
228 puts("Board: Grinn liteBoard\n");
233 #ifdef CONFIG_SPL_BUILD
234 void board_boot_order(u32 *spl_boot_list)
236 struct src *psrc = (struct src *)SRC_BASE_ADDR;
237 unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
238 unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
239 unsigned port = (reg >> 11) & 0x1;
242 spl_boot_list[0] = BOOT_DEVICE_MMC1;
243 spl_boot_list[1] = BOOT_DEVICE_MMC2;
245 spl_boot_list[0] = BOOT_DEVICE_MMC2;
246 spl_boot_list[1] = BOOT_DEVICE_MMC1;
250 void board_init_f(ulong dummy)