1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2015 Google, Inc
9 #include <asm/arch-rockchip/clock.h>
10 #include <dt-bindings/clock/rk3288-cru.h>
11 #include <linux/err.h>
12 #include <power/regulator.h>
15 * We should increase the DDR voltage to 1.2V using the PWM regulator.
16 * There is a U-Boot driver for this but it may need to add support for the
17 * 'voltage-table' property.
19 #ifndef CONFIG_SPL_BUILD
20 #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
21 static int veyron_init(void)
27 ret = regulator_get_by_platname("vdd_arm", &dev);
29 debug("Cannot set regulator name\n");
33 /* Slowly raise to max CPU voltage to prevent overshoot */
34 ret = regulator_set_value(dev, 1200000);
37 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
38 ret = regulator_set_value(dev, 1400000);
41 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
43 ret = rockchip_get_clk(&clk.dev);
47 ret = clk_set_rate(&clk, 1800000000);
48 if (IS_ERR_VALUE(ret))
51 ret = regulator_get_by_platname("vcc33_sd", &dev);
53 debug("Cannot get regulator name\n");
57 ret = regulator_set_value(dev, 3300000);
61 ret = regulators_enable_boot_on(false);
63 debug("%s: Cannot enable boot on regulators\n", __func__);
71 int board_early_init_f(void)
76 #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
77 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
84 * This init is done in SPL, but when chain-loading U-Boot SPL will
85 * have been skipped. Allow the clock driver to check if it needs
88 ret = rockchip_get_clk(&dev);
90 debug("CLK init failed: %d\n", ret);