4 * The GENIETV is using the following physical memorymap (copied from
5 * the FADS configuration):
7 * ff020000 -> ff02ffff : pcmcia
8 * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM
9 * ff000000 -> ff00ffff : IMAP internal in the cpu
10 * 02800000 -> 0287ffff : flash connected to CS0
11 * 00000000 -> nnnnnnnn : sdram setup by U-Boot
13 * CS pins are connected as follows:
15 * CS0 -512Kb boot flash
20 * CS5 - LON (if present)
24 * Ports are configured as follows:
26 * PA7 - SDRAM banks enable
32 #define CFG_PA7 0x0100
34 /* ------------------------------------------------------------------------- */
36 static long int dram_size (long int, long int *, long int);
38 /* ------------------------------------------------------------------------- */
40 #define _NOT_USED_ 0xFFFFFFFF
42 const uint sdram_table[] =
45 * Single Read. (Offset 0 in UPMB RAM)
47 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBEEC00,
48 0x1FFDDC47, /* last */
50 * SDRAM Initialization (offset 5 in UPMB RAM)
52 * This is no UPM entry point. The following definition uses
53 * the remaining space to establish an initialization
54 * sequence, which is executed by a RUN command.
57 0x1FFDDC34, 0xEFEEAC34, 0x1FBD5C35, /* last */
59 * Burst Read. (Offset 8 in UPMB RAM)
61 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
62 0xF0AFFC00, 0xF1AFFC00, 0xEFBEEC00, 0x1FFDDC47, /* last */
63 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
64 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66 * Single Write. (Offset 18 in UPMB RAM)
68 0x1F2DFC04, 0xEEAFAC00, 0x01BE4C04, 0x1FFDDC47, /* last */
69 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
71 * Burst Write. (Offset 20 in UPMB RAM)
73 0x1F0DFC04, 0xEEAFAC00, 0x10AF5C00, 0xF0AFFC00,
74 0xF0AFFC00, 0xE1BEEC04, 0x1FFDDC47, /* last */
76 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
77 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
79 * Refresh (Offset 30 in UPMB RAM)
81 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
82 0xFFFFFC84, 0xFFFFFC07, /* last */
83 _NOT_USED_, _NOT_USED_,
84 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
86 * Exception. (Offset 3c in UPMB RAM)
88 0x7FFFFC07, /* last */
89 _NOT_USED_, _NOT_USED_, _NOT_USED_,
92 /* ------------------------------------------------------------------------- */
96 * Check Board Identity
101 puts ("Board: GenieTV\n");
106 static void PrintState(void)
108 volatile immap_t *im = (immap_t *)CFG_IMMR;
109 volatile memctl8xx_t *memctl = &im->im_memctl;
111 printf("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0, memctl->memc_or0);
112 printf("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1, memctl->memc_or1);
113 printf("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2, memctl->memc_or2);
117 /* ------------------------------------------------------------------------- */
119 long int initdram (int board_type)
121 volatile immap_t *im = (immap_t *)CFG_IMMR;
122 volatile memctl8xx_t *memctl = &im->im_memctl;
123 long int size_b0, size_b1, size8;
127 /* Configuring PA7 for general purpouse output pin */
128 im->im_ioport.iop_papar &= ~CFG_PA7 ; /* 0 = general purpouse */
129 im->im_ioport.iop_padir |= CFG_PA7 ; /* 1 = output */
131 /* Enable SDRAM - PA7 = 1 */
132 im->im_ioport.iop_padat |= CFG_PA7 ; /* value of PA7 */
135 * Preliminary prescaler for refresh (depends on number of
136 * banks): This value is selected for four cycles every 62.4 us
137 * with two SDRAM banks or four cycles every 31.2 us with one
138 * bank. It will be adjusted after memory sizing.
140 memctl->memc_mptpr = CFG_MPTPR_2BK_4K ;
142 memctl->memc_mbmr = CFG_MBMR_8COL;
144 upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
147 * Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at
148 * preliminary addresses - these have to be modified after the
149 * SDRAM size has been determined.
152 memctl->memc_or1 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
153 memctl->memc_br1 = ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
155 memctl->memc_or2 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
156 memctl->memc_br2 = ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
158 /* perform SDRAM initialization sequence */
159 memctl->memc_mar = 0x00000088;
161 memctl->memc_mcr = 0x80802105; /* SDRAM bank 0 */
163 memctl->memc_mcr = 0x80804105; /* SDRAM bank 1 */
165 /* Execute refresh 8 times */
166 memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X ;
168 memctl->memc_mcr = 0x80802130; /* SDRAM bank 0 - execute twice */
170 memctl->memc_mcr = 0x80804130; /* SDRAM bank 1 - execute twice */
172 /* Execute refresh 4 times */
173 memctl->memc_mbmr = CFG_MBMR_8COL;
176 * Check Bank 0 Memory Size for re-configuration
184 /* printf ("\nChecking bank1..."); */
185 size8 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
189 /* printf ("\nChecking bank2..."); */
190 size_b1 = dram_size (memctl->memc_mbmr, (ulong *)SDRAM_BASE2_PRELIM,SDRAM_MAX_SIZE);
193 * Final mapping: map bigger bank first
196 memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
197 memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
202 * Position Bank 1 immediately above Bank 0
204 memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
205 memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) +
206 (size_b0 & BR_BA_MSK);
215 memctl->memc_br2 = 0;
216 /* adjust refresh rate depending on SDRAM type, one bank */
217 memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
220 /* If no memory detected, disable SDRAM */
221 if ((size_b0 + size_b1) == 0)
223 printf("disabling SDRAM!\n");
224 /* Disable SDRAM - PA7 = 1 */
225 im->im_ioport.iop_padat &= ~CFG_PA7 ; /* value of PA7 */
228 /* printf("done! (%08lx)\n", size_b0 + size_b1); */
233 return (size_b0 + size_b1);
236 /* ------------------------------------------------------------------------- */
239 * Check memory range for valid RAM. A simple memory test determines
240 * the actually available RAM size between addresses `base' and
241 * `base + maxsize'. Some (not all) hardware errors are detected:
242 * - short between address lines
243 * - short between data lines
246 static long int dram_size (long int mbmr_value, long int *base, long int maxsize)
248 volatile long int *addr;
251 /*memctl->memc_mbmr = mbmr_value; */
253 for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
254 addr = base + cnt; /* pointer arith! */
259 /* write 0 to base address */
263 /* check at base address */
264 if ((val = *addr) != 0) {
269 for (cnt = 1; ; cnt <<= 1) {
270 addr = base + cnt; /* pointer arith! */
274 /* printf("(%08lx)", cnt*sizeof(long)); */
275 return (cnt * sizeof(long));
282 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
284 #ifdef CFG_PCMCIA_MEM_ADDR
285 volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
288 int pcmcia_init(void)
290 volatile pcmconf8xx_t *pcmp;
291 uint v, slota, slotb;
294 ** Enable the PCMCIA for a Flash card.
296 pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
299 pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR;
300 pcmp->pcmc_por0 = 0xc00ff05d;
303 /* Set all slots to zero by default. */
304 pcmp->pcmc_pgcra = 0;
305 pcmp->pcmc_pgcrb = 0;
307 pcmp->pcmc_pgcra = 0x40;
310 pcmp->pcmc_pgcrb = 0x40;
313 /* Check if any PCMCIA card is luged in. */
314 slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
315 slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
317 if (!(slota || slotb))
319 printf("No card present\n");
321 pcmp->pcmc_pgcra = 0;
324 pcmp->pcmc_pgcrb = 0;
329 printf("Unknown card (");
333 switch( (pcmp->pcmc_pipr >> 14) & 3 )
344 printf("5V, 3V and x.xV");
351 printf("; using 3V");
352 /* Enable 3 volt Vcc. */
357 printf("; unknown voltage");
361 /* disable pcmcia reset after a while */
365 pcmp->pcmc_pgcrb = 0;
367 /* If you using a real hd you should give a short
369 #ifdef CONFIG_DISK_SPINUP_TIME
370 udelay(CONFIG_DISK_SPINUP_TIME);
375 #endif /* CFG_CMD_PCMCIA */