1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017 General Electric Company
5 * Based on board/freescale/mx53loco/mx53loco.c:
7 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 * Jason Liu <r64343@freescale.com>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/iomux-mx53.h>
18 #include <asm/arch/clock.h>
19 #include <linux/errno.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/mx5_video.h>
22 #include <environment.h>
26 #include <fsl_esdhc.h>
28 #include <power/pmic.h>
29 #include <dialog_pmic.h>
32 #include <ipu_pixfmt.h>
36 #include "../../ge/common/ge_common.h"
37 #include "../../ge/common/vpd_reader.h"
39 #define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24)
41 DECLARE_GLOBAL_DATA_PTR;
43 /* Index of I2C1, SEGMENT 1 (see CONFIG_SYS_I2C_BUSES). */
44 #define VPD_EEPROM_BUS 2
46 /* Address of 24C08 EEPROM. */
47 #define VPD_EEPROM_ADDR 0x50
48 #define VPD_EEPROM_ADDR_LEN 1
50 static u32 mx53_dram_size[2];
52 phys_size_t get_effective_memsize(void)
55 * WARNING: We must override get_effective_memsize() function here
56 * to report only the size of the first DRAM bank. This is to make
57 * U-Boot relocator place U-Boot into valid memory, that is, at the
58 * end of the first DRAM bank. If we did not override this function
59 * like so, U-Boot would be placed at the address of the first DRAM
60 * bank + total DRAM size - sizeof(uboot), which in the setup where
61 * each DRAM bank contains 512MiB of DRAM would result in placing
62 * U-Boot into invalid memory area close to the end of the first
65 return mx53_dram_size[0];
70 mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
71 mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
73 gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
78 int dram_init_banksize(void)
80 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
81 gd->bd->bi_dram[0].size = mx53_dram_size[0];
83 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
84 gd->bd->bi_dram[1].size = mx53_dram_size[1];
89 u32 get_board_rev(void)
91 return get_cpu_rev() & ~(0xF << 8);
94 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
95 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
97 #ifdef CONFIG_USB_EHCI_MX5
98 int board_ehci_hcd_init(int port)
100 /* request VBUS power enable pin, GPIO7_8 */
101 imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
102 gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
107 static void setup_iomux_fec(void)
109 static const iomux_v3_cfg_t fec_pads[] = {
110 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
111 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP |
113 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
114 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
115 PAD_CTL_HYS | PAD_CTL_PKE),
116 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
117 PAD_CTL_HYS | PAD_CTL_PKE),
118 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
119 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
120 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
121 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
122 PAD_CTL_HYS | PAD_CTL_PKE),
123 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
124 PAD_CTL_HYS | PAD_CTL_PKE),
125 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
126 PAD_CTL_HYS | PAD_CTL_PKE),
129 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
132 #ifdef CONFIG_FSL_ESDHC
133 struct fsl_esdhc_cfg esdhc_cfg[2] = {
134 {MMC_SDHC3_BASE_ADDR},
135 {MMC_SDHC1_BASE_ADDR},
138 int board_mmc_getcd(struct mmc *mmc)
143 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
145 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
148 int board_mmc_init(bd_t *bis)
150 static const iomux_v3_cfg_t sd1_pads[] = {
151 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
153 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
154 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
155 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
156 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
157 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
158 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
159 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
160 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
161 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
162 MX53_PAD_EIM_DA11__GPIO3_11,
165 static const iomux_v3_cfg_t sd2_pads[] = {
166 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
167 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
168 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
169 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
170 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
171 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
172 MX53_PAD_EIM_DA13__GPIO3_13,
178 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
179 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
181 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
184 imx_iomux_v3_setup_multiple_pads(sd1_pads,
185 ARRAY_SIZE(sd1_pads));
188 imx_iomux_v3_setup_multiple_pads(sd2_pads,
189 ARRAY_SIZE(sd2_pads));
192 printf("Warning: you configured more ESDHC controller (%d) as supported by the board(2)\n",
193 CONFIG_SYS_FSL_ESDHC_NUM);
196 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
205 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
206 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
208 static void setup_iomux_i2c(void)
210 static const iomux_v3_cfg_t i2c1_pads[] = {
211 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
212 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
215 imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
218 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
220 static struct i2c_pads_info i2c_pad_info1 = {
222 .i2c_mode = MX53_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
223 .gpio_mode = MX53_PAD_EIM_D28__GPIO3_28 | I2C_PAD,
224 .gp = IMX_GPIO_NR(3, 28)
227 .i2c_mode = MX53_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
228 .gpio_mode = MX53_PAD_EIM_D21__GPIO3_21 | I2C_PAD,
229 .gp = IMX_GPIO_NR(3, 21)
233 static int clock_1GHz(void)
236 u32 ref_clk = MXC_HCLK;
238 * After increasing voltage to 1.25V, we can switch
239 * CPU clock to 1GHz and DDR to 400MHz safely
241 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
243 printf("CPU: Switch CPU clock to 1GHZ failed\n");
247 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
248 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
250 printf("CPU: Switch DDR clock to 400MHz failed\n");
257 void ppd_gpio_init(void)
261 imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads));
262 for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i)
263 gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value);
266 int board_early_init_f(void)
276 * Do not overwrite the console
277 * Use always serial for U-Boot console
279 int overwrite_console(void)
284 #define VPD_TYPE_INVALID 0x00
285 #define VPD_BLOCK_NETWORK 0x20
286 #define VPD_BLOCK_HWID 0x44
287 #define VPD_PRODUCT_PPD 4
288 #define VPD_HAS_MAC1 0x1
289 #define VPD_MAC_ADDRESS_LENGTH 6
294 unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
298 * Extracts MAC and product information from the VPD.
300 static int vpd_callback(void *userdata, u8 id, u8 version, u8 type, size_t size,
303 struct vpd_cache *vpd = (struct vpd_cache *)userdata;
305 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
307 vpd->product_id = data[0];
309 } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
310 type != VPD_TYPE_INVALID) {
312 vpd->has |= VPD_HAS_MAC1;
313 memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
320 static void process_vpd(struct vpd_cache *vpd)
324 if (vpd->product_id == VPD_PRODUCT_PPD)
327 if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
328 eth_env_set_enetaddr("ethaddr", vpd->mac1);
331 static int read_vpd(void)
333 struct vpd_cache vpd;
337 unsigned int current_i2c_bus = i2c_get_bus_num();
339 res = i2c_set_bus_num(VPD_EEPROM_BUS);
347 res = i2c_read(VPD_EEPROM_ADDR, 0, VPD_EEPROM_ADDR_LEN, data, size);
349 memset(&vpd, 0, sizeof(vpd));
350 vpd_reader(size, data, &vpd, vpd_callback);
356 i2c_set_bus_num(current_i2c_bus);
362 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
364 mxc_set_sata_internal_clock();
367 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
372 int misc_init_r(void)
376 /* We care about WDOG only, treating everything else as
379 if (get_imx_reset_cause() & 0x0010)
384 env_set("bootcause", cause);
389 int board_late_init(void)
409 puts("Board: GE PPD\n");