board/ge/bx50v3/bx50v3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Timesys Corporation
   4  * Copyright 2015 General Electric Company
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/mx6-pins.h>
  12 #include <linux/errno.h>
  13 #include <asm/gpio.h>
  14 #include <asm/mach-imx/mxc_i2c.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/mach-imx/video.h>
  18 #include <mmc.h>
  19 #include <fsl_esdhc.h>
  20 #include <miiphy.h>
  21 #include <net.h>
  22 #include <netdev.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <i2c.h>
  28 #include <input.h>
  29 #include <pwm.h>
  30 #include <stdlib.h>
  31 #include "../common/ge_common.h"
  32 #include "../common/vpd_reader.h"
  33 #include "../../../drivers/net/e1000.h"
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 static int confidx = 3;  /* Default to b850v3. */
  37 static struct vpd_cache vpd;
  38
  39 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  40         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  41         PAD_CTL_HYS)
  42
  43 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  44         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  45         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  46
  47 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  48         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  49
  50 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  51         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  52
  53 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  54         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  55
  56 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  57                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  58
  59 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  61         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  62
  63 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  64
  65 int dram_init(void)
  66 {
  67         gd->ram_size = imx_ddr_size();
  68
  69         return 0;
  70 }
  71
  72 static iomux_v3_cfg_t const uart3_pads[] = {
  73         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  74         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  75         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  76         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  77 };
  78
  79 static iomux_v3_cfg_t const uart4_pads[] = {
  80         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  81         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  82 };
  83
  84 static iomux_v3_cfg_t const enet_pads[] = {
  85         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86         MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  94         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  95         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  96         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  97         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  98         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  99         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 100         /* AR8033 PHY Reset */
 101         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 102 };
 103
 104 static void setup_iomux_enet(void)
 105 {
 106         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 107
 108         /* Reset AR8033 PHY */
 109         gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
 110         mdelay(10);
 111         gpio_set_value(IMX_GPIO_NR(1, 28), 1);
 112         mdelay(1);
 113 }
 114
 115 static iomux_v3_cfg_t const ecspi1_pads[] = {
 116         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 117         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 118         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 119         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 120 };
 121
 122 static struct i2c_pads_info i2c_pad_info1 = {
 123         .scl = {
 124                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
 125                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
 126                 .gp = IMX_GPIO_NR(5, 27)
 127         },
 128         .sda = {
 129                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
 130                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
 131                 .gp = IMX_GPIO_NR(5, 26)
 132         }
 133 };
 134
 135 static struct i2c_pads_info i2c_pad_info2 = {
 136         .scl = {
 137                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 138                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 139                 .gp = IMX_GPIO_NR(4, 12)
 140         },
 141         .sda = {
 142                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 143                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 144                 .gp = IMX_GPIO_NR(4, 13)
 145         }
 146 };
 147
 148 static struct i2c_pads_info i2c_pad_info3 = {
 149         .scl = {
 150                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
 151                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
 152                 .gp = IMX_GPIO_NR(1, 3)
 153         },
 154         .sda = {
 155                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 156                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 157                 .gp = IMX_GPIO_NR(1, 6)
 158         }
 159 };
 160
 161 #ifdef CONFIG_MXC_SPI
 162 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 163 {
 164         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
 165 }
 166
 167 static void setup_spi(void)
 168 {
 169         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 170 }
 171 #endif
 172
 173 static iomux_v3_cfg_t const pcie_pads[] = {
 174         MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 175         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 176 };
 177
 178 static void setup_pcie(void)
 179 {
 180         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 181 }
 182
 183 static void setup_iomux_uart(void)
 184 {
 185         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 186         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 187 }
 188
 189 static int mx6_rgmii_rework(struct phy_device *phydev)
 190 {
 191         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
 192         /* set device address 0x7 */
 193         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 194         /* offset 0x8016: CLK_25M Clock Select */
 195         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 196         /* enable register write, no post increment, address 0x7 */
 197         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 198         /* set to 125 MHz from local PLL source */
 199         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 200
 201         /* rgmii tx clock delay enable */
 202         /* set debug port address: SerDes Test and System Mode Control */
 203         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 204         /* enable rgmii tx clock delay */
 205         /* set the reserved bits to avoid board specific voltage peak issue*/
 206         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 207
 208         return 0;
 209 }
 210
 211 int board_phy_config(struct phy_device *phydev)
 212 {
 213         mx6_rgmii_rework(phydev);
 214
 215         if (phydev->drv->config)
 216                 phydev->drv->config(phydev);
 217
 218         return 0;
 219 }
 220
 221 #if defined(CONFIG_VIDEO_IPUV3)
 222 static iomux_v3_cfg_t const backlight_pads[] = {
 223         /* Power for LVDS Display */
 224         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 225 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 226         /* Backlight enable for LVDS display */
 227         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 228 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 229         /* backlight PWM brightness control */
 230         MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 231 };
 232
 233 static void do_enable_hdmi(struct display_info_t const *dev)
 234 {
 235         imx_enable_hdmi_phy();
 236 }
 237
 238 int board_cfb_skip(void)
 239 {
 240         gpio_direction_output(LVDS_POWER_GP, 1);
 241
 242         return 0;
 243 }
 244
 245 static int is_b850v3(void)
 246 {
 247         return confidx == 3;
 248 }
 249
 250 static int detect_lcd(struct display_info_t const *dev)
 251 {
 252         return !is_b850v3();
 253 }
 254
 255 struct display_info_t const displays[] = {{
 256         .bus    = -1,
 257         .addr   = -1,
 258         .pixfmt = IPU_PIX_FMT_RGB24,
 259         .detect = detect_lcd,
 260         .enable = NULL,
 261         .mode   = {
 262                 .name           = "G121X1-L03",
 263                 .refresh        = 60,
 264                 .xres           = 1024,
 265                 .yres           = 768,
 266                 .pixclock       = 15385,
 267                 .left_margin    = 20,
 268                 .right_margin   = 300,
 269                 .upper_margin   = 30,
 270                 .lower_margin   = 8,
 271                 .hsync_len      = 1,
 272                 .vsync_len      = 1,
 273                 .sync           = FB_SYNC_EXT,
 274                 .vmode          = FB_VMODE_NONINTERLACED
 275 } }, {
 276         .bus    = -1,
 277         .addr   = 3,
 278         .pixfmt = IPU_PIX_FMT_RGB24,
 279         .detect = detect_hdmi,
 280         .enable = do_enable_hdmi,
 281         .mode   = {
 282                 .name           = "HDMI",
 283                 .refresh        = 60,
 284                 .xres           = 1024,
 285                 .yres           = 768,
 286                 .pixclock       = 15385,
 287                 .left_margin    = 220,
 288                 .right_margin   = 40,
 289                 .upper_margin   = 21,
 290                 .lower_margin   = 7,
 291                 .hsync_len      = 60,
 292                 .vsync_len      = 10,
 293                 .sync           = FB_SYNC_EXT,
 294                 .vmode          = FB_VMODE_NONINTERLACED
 295 } } };
 296 size_t display_count = ARRAY_SIZE(displays);
 297
 298 static void enable_videopll(void)
 299 {
 300         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 301         s32 timeout = 100000;
 302
 303         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 304
 305         /* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
 306          *   |
 307          * PLL5
 308          *   |
 309          * CS2CDR[LDB_DI0_CLK_SEL]
 310          *   |
 311          *   +----> LDB_DI0_SERIAL_CLK_ROOT
 312          *   |
 313          *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
 314          */
 315
 316         clrsetbits_le32(&ccm->analog_pll_video,
 317                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 318                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 319                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 320                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 321
 322         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 323         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 324
 325         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 326
 327         while (timeout--)
 328                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 329                         break;
 330
 331         if (timeout < 0)
 332                 printf("Warning: video pll lock timeout!\n");
 333
 334         clrsetbits_le32(&ccm->analog_pll_video,
 335                         BM_ANADIG_PLL_VIDEO_BYPASS,
 336                         BM_ANADIG_PLL_VIDEO_ENABLE);
 337 }
 338
 339 static void setup_display_b850v3(void)
 340 {
 341         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 342         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 343
 344         enable_videopll();
 345
 346         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 347         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 348
 349         imx_setup_hdmi();
 350
 351         /* Set LDB_DI0 as clock source for IPU_DI0 */
 352         clrsetbits_le32(&mxc_ccm->chsccdr,
 353                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 354                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 355                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 356
 357         /* Turn on IPU LDB DI0 clocks */
 358         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 359
 360         enable_ipu_clock();
 361
 362         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 363                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 364                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 365                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 366                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 367                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 368                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 369                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 370                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 371                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 372                &iomux->gpr[2]);
 373
 374         clrbits_le32(&iomux->gpr[3],
 375                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 376                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 377                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 378 }
 379
 380 static void setup_display_bx50v3(void)
 381 {
 382         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 383         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 384
 385         enable_videopll();
 386
 387         /* When a reset/reboot is performed the display power needs to be turned
 388          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 389          * an additional 200ms here. Unfortunately we use external PMIC for
 390          * doing the reset, so can not differentiate between POR vs soft reset
 391          */
 392         mdelay(200);
 393
 394         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 395         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 396
 397         /* Set LDB_DI0 as clock source for IPU_DI0 */
 398         clrsetbits_le32(&mxc_ccm->chsccdr,
 399                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 400                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 401                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 402
 403         /* Turn on IPU LDB DI0 clocks */
 404         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 405
 406         enable_ipu_clock();
 407
 408         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 409                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 410                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 411                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 412                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 413                &iomux->gpr[2]);
 414
 415         clrsetbits_le32(&iomux->gpr[3],
 416                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 417                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 418                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 419
 420         /* backlights off until needed */
 421         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 422                                          ARRAY_SIZE(backlight_pads));
 423         gpio_direction_input(LVDS_POWER_GP);
 424         gpio_direction_input(LVDS_BACKLIGHT_GP);
 425 }
 426 #endif /* CONFIG_VIDEO_IPUV3 */
 427
 428 /*
 429  * Do not overwrite the console
 430  * Use always serial for U-Boot console
 431  */
 432 int overwrite_console(void)
 433 {
 434         return 1;
 435 }
 436
 437 #define VPD_TYPE_INVALID 0x00
 438 #define VPD_BLOCK_NETWORK 0x20
 439 #define VPD_BLOCK_HWID 0x44
 440 #define VPD_PRODUCT_B850 1
 441 #define VPD_PRODUCT_B650 2
 442 #define VPD_PRODUCT_B450 3
 443 #define VPD_HAS_MAC1 0x1
 444 #define VPD_HAS_MAC2 0x2
 445 #define VPD_MAC_ADDRESS_LENGTH 6
 446
 447 struct vpd_cache {
 448         bool is_read;
 449         u8 product_id;
 450         u8 has;
 451         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 452         unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
 453 };
 454
 455 /*
 456  * Extracts MAC and product information from the VPD.
 457  */
 458 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
 459                         size_t size, u8 const *data)
 460 {
 461         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 462             size >= 1) {
 463                 vpd->product_id = data[0];
 464         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 465                    type != VPD_TYPE_INVALID) {
 466                 if (size >= 6) {
 467                         vpd->has |= VPD_HAS_MAC1;
 468                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 469                 }
 470                 if (size >= 12) {
 471                         vpd->has |= VPD_HAS_MAC2;
 472                         memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
 473                 }
 474         }
 475
 476         return 0;
 477 }
 478
 479 static void process_vpd(struct vpd_cache *vpd)
 480 {
 481         int fec_index = -1;
 482         int i210_index = -1;
 483
 484         if (!vpd->is_read) {
 485                 printf("VPD wasn't read");
 486                 return;
 487         }
 488
 489         switch (vpd->product_id) {
 490         case VPD_PRODUCT_B450:
 491                 env_set("confidx", "1");
 492                 i210_index = 0;
 493                 fec_index = 1;
 494                 break;
 495         case VPD_PRODUCT_B650:
 496                 env_set("confidx", "2");
 497                 i210_index = 0;
 498                 fec_index = 1;
 499                 break;
 500         case VPD_PRODUCT_B850:
 501                 env_set("confidx", "3");
 502                 i210_index = 1;
 503                 fec_index = 2;
 504                 break;
 505         }
 506
 507         if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
 508                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 509
 510         if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 511                 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 512 }
 513
 514 int board_eth_init(bd_t *bis)
 515 {
 516         setup_iomux_enet();
 517         setup_pcie();
 518
 519         e1000_initialize(bis);
 520
 521         return cpu_eth_init(bis);
 522 }
 523
 524 static iomux_v3_cfg_t const misc_pads[] = {
 525         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 526         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 527         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 528         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 529         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 530         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 531         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 532         MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 533 };
 534 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 535 #define WIFI_EN IMX_GPIO_NR(6, 14)
 536
 537 int board_early_init_f(void)
 538 {
 539         imx_iomux_v3_setup_multiple_pads(misc_pads,
 540                                          ARRAY_SIZE(misc_pads));
 541
 542         setup_iomux_uart();
 543
 544 #if defined(CONFIG_VIDEO_IPUV3)
 545         /* Set LDB clock to Video PLL */
 546         select_ldb_di_clock_source(MXC_PLL5_CLK);
 547 #endif
 548         return 0;
 549 }
 550
 551 static void set_confidx(const struct vpd_cache* vpd)
 552 {
 553         switch (vpd->product_id) {
 554         case VPD_PRODUCT_B450:
 555                 confidx = 1;
 556                 break;
 557         case VPD_PRODUCT_B650:
 558                 confidx = 2;
 559                 break;
 560         case VPD_PRODUCT_B850:
 561                 confidx = 3;
 562                 break;
 563         }
 564 }
 565
 566 int board_init(void)
 567 {
 568         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 569         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 570         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 571
 572         if (!read_vpd(&vpd, vpd_callback)) {
 573                 vpd.is_read = true;
 574                 set_confidx(&vpd);
 575         }
 576
 577         gpio_direction_output(SUS_S3_OUT, 1);
 578         gpio_direction_output(WIFI_EN, 1);
 579 #if defined(CONFIG_VIDEO_IPUV3)
 580         if (is_b850v3())
 581                 setup_display_b850v3();
 582         else
 583                 setup_display_bx50v3();
 584 #endif
 585         /* address of boot parameters */
 586         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 587
 588 #ifdef CONFIG_MXC_SPI
 589         setup_spi();
 590 #endif
 591         return 0;
 592 }
 593
 594 #ifdef CONFIG_CMD_BMODE
 595 static const struct boot_mode board_boot_modes[] = {
 596         /* 4 bit bus width */
 597         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 598         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 599         {NULL,   0},
 600 };
 601 #endif
 602
 603 void pmic_init(void)
 604 {
 605 #define I2C_PMIC                0x2
 606 #define DA9063_I2C_ADDR         0x58
 607 #define DA9063_REG_BCORE2_CFG   0x9D
 608 #define DA9063_REG_BCORE1_CFG   0x9E
 609 #define DA9063_REG_BPRO_CFG     0x9F
 610 #define DA9063_REG_BIO_CFG      0xA0
 611 #define DA9063_REG_BMEM_CFG     0xA1
 612 #define DA9063_REG_BPERI_CFG    0xA2
 613 #define DA9063_BUCK_MODE_MASK   0xC0
 614 #define DA9063_BUCK_MODE_MANUAL 0x00
 615 #define DA9063_BUCK_MODE_SLEEP  0x40
 616 #define DA9063_BUCK_MODE_SYNC   0x80
 617 #define DA9063_BUCK_MODE_AUTO   0xC0
 618
 619         uchar val;
 620
 621         i2c_set_bus_num(I2C_PMIC);
 622
 623         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 624         val &= ~DA9063_BUCK_MODE_MASK;
 625         val |= DA9063_BUCK_MODE_SYNC;
 626         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 627
 628         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 629         val &= ~DA9063_BUCK_MODE_MASK;
 630         val |= DA9063_BUCK_MODE_SYNC;
 631         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 632
 633         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 634         val &= ~DA9063_BUCK_MODE_MASK;
 635         val |= DA9063_BUCK_MODE_SYNC;
 636         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 637
 638         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 639         val &= ~DA9063_BUCK_MODE_MASK;
 640         val |= DA9063_BUCK_MODE_SYNC;
 641         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 642
 643         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 644         val &= ~DA9063_BUCK_MODE_MASK;
 645         val |= DA9063_BUCK_MODE_SYNC;
 646         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 647
 648         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 649         val &= ~DA9063_BUCK_MODE_MASK;
 650         val |= DA9063_BUCK_MODE_SYNC;
 651         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 652 }
 653
 654 int board_late_init(void)
 655 {
 656         process_vpd(&vpd);
 657
 658 #ifdef CONFIG_CMD_BMODE
 659         add_board_boot_modes(board_boot_modes);
 660 #endif
 661
 662         if (is_b850v3())
 663                 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
 664         else
 665                 env_set("videoargs", "video=LVDS-1:1024x768@65");
 666
 667         /* board specific pmic init */
 668         pmic_init();
 669
 670         check_time();
 671
 672         return 0;
 673 }
 674
 675 /*
 676  * Removes the 'eth[0-9]*addr' environment variable with the given index
 677  *
 678  * @param index [in] the index of the eth_device whose variable is to be removed
 679  */
 680 static void remove_ethaddr_env_var(int index)
 681 {
 682         char env_var_name[9];
 683
 684         sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
 685         env_set(env_var_name, NULL);
 686 }
 687
 688 int last_stage_init(void)
 689 {
 690         int i;
 691
 692         /*
 693          * Remove first three ethaddr which may have been created by
 694          * function process_vpd().
 695          */
 696         for (i = 0; i < 3; ++i)
 697                 remove_ethaddr_env_var(i);
 698
 699         return 0;
 700 }
 701
 702 int checkboard(void)
 703 {
 704         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 705         return 0;
 706 }
 707
 708 static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 709 {
 710 #ifdef CONFIG_VIDEO_IPUV3
 711         /* We need at least 200ms between power on and backlight on
 712          * as per specifications from CHI MEI */
 713         mdelay(250);
 714
 715         /* enable backlight PWM 1 */
 716         pwm_init(0, 0, 0);
 717
 718         /* duty cycle 5000000ns, period: 5000000ns */
 719         pwm_config(0, 5000000, 5000000);
 720
 721         /* Backlight Power */
 722         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 723
 724         pwm_enable(0);
 725 #endif
 726
 727         return 0;
 728 }
 729
 730 U_BOOT_CMD(
 731        bx50_backlight_enable, 1,      1,      do_backlight_enable,
 732        "enable Bx50 backlight",
 733        ""
 734 );