board/ge/bx50v3/bx50v3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Timesys Corporation
   4  * Copyright 2015 General Electric Company
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <init.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <env.h>
  14 #include <linux/errno.h>
  15 #include <linux/libfdt.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/mxc_i2c.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/video.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <miiphy.h>
  24 #include <net.h>
  25 #include <netdev.h>
  26 #include <asm/arch/mxc_hdmi.h>
  27 #include <asm/arch/crm_regs.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <i2c.h>
  31 #include <input.h>
  32 #include <pwm.h>
  33 #include <version.h>
  34 #include <stdlib.h>
  35 #include <dm/root.h>
  36 #include "../common/ge_common.h"
  37 #include "../common/vpd_reader.h"
  38 #include "../../../drivers/net/e1000.h"
  39 #include <pci.h>
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 static int confidx;  /* Default to generic. */
  44 static struct vpd_cache vpd;
  45
  46 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  48         PAD_CTL_HYS)
  49
  50 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  51         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  52         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  53
  54 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  55         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  56
  57 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  58         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  59
  60 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  61         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  62
  63 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  64         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  65         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  66
  67 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  68
  69 int dram_init(void)
  70 {
  71         gd->ram_size = imx_ddr_size();
  72
  73         return 0;
  74 }
  75
  76 static iomux_v3_cfg_t const uart3_pads[] = {
  77         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  78         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  79         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  80         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  81 };
  82
  83 static iomux_v3_cfg_t const uart4_pads[] = {
  84         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  85         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  86 };
  87
  88 static struct i2c_pads_info i2c_pad_info1 = {
  89         .scl = {
  90                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
  91                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
  92                 .gp = IMX_GPIO_NR(5, 27)
  93         },
  94         .sda = {
  95                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
  96                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
  97                 .gp = IMX_GPIO_NR(5, 26)
  98         }
  99 };
 100
 101 static struct i2c_pads_info i2c_pad_info2 = {
 102         .scl = {
 103                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 104                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 105                 .gp = IMX_GPIO_NR(4, 12)
 106         },
 107         .sda = {
 108                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 109                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 110                 .gp = IMX_GPIO_NR(4, 13)
 111         }
 112 };
 113
 114 static struct i2c_pads_info i2c_pad_info3 = {
 115         .scl = {
 116                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
 117                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
 118                 .gp = IMX_GPIO_NR(1, 3)
 119         },
 120         .sda = {
 121                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 122                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 123                 .gp = IMX_GPIO_NR(1, 6)
 124         }
 125 };
 126
 127 static void setup_iomux_uart(void)
 128 {
 129         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 130         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 131 }
 132
 133 static int mx6_rgmii_rework(struct phy_device *phydev)
 134 {
 135         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
 136         /* set device address 0x7 */
 137         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 138         /* offset 0x8016: CLK_25M Clock Select */
 139         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 140         /* enable register write, no post increment, address 0x7 */
 141         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 142         /* set to 125 MHz from local PLL source */
 143         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 144
 145         /* rgmii tx clock delay enable */
 146         /* set debug port address: SerDes Test and System Mode Control */
 147         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 148         /* enable rgmii tx clock delay */
 149         /* set the reserved bits to avoid board specific voltage peak issue*/
 150         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 151
 152         return 0;
 153 }
 154
 155 int board_phy_config(struct phy_device *phydev)
 156 {
 157         mx6_rgmii_rework(phydev);
 158
 159         if (phydev->drv->config)
 160                 phydev->drv->config(phydev);
 161
 162         return 0;
 163 }
 164
 165 #if defined(CONFIG_VIDEO_IPUV3)
 166 static iomux_v3_cfg_t const backlight_pads[] = {
 167         /* Power for LVDS Display */
 168         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 169 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 170         /* Backlight enable for LVDS display */
 171         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 172 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 173         /* backlight PWM brightness control */
 174         MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 175 };
 176
 177 static void do_enable_hdmi(struct display_info_t const *dev)
 178 {
 179         imx_enable_hdmi_phy();
 180 }
 181
 182 static int is_b850v3(void)
 183 {
 184         return confidx == 3;
 185 }
 186
 187 static int detect_lcd(struct display_info_t const *dev)
 188 {
 189         return !is_b850v3();
 190 }
 191
 192 struct display_info_t const displays[] = {{
 193         .bus    = -1,
 194         .addr   = -1,
 195         .pixfmt = IPU_PIX_FMT_RGB24,
 196         .detect = detect_lcd,
 197         .enable = NULL,
 198         .mode   = {
 199                 .name           = "G121X1-L03",
 200                 .refresh        = 60,
 201                 .xres           = 1024,
 202                 .yres           = 768,
 203                 .pixclock       = 15385,
 204                 .left_margin    = 20,
 205                 .right_margin   = 300,
 206                 .upper_margin   = 30,
 207                 .lower_margin   = 8,
 208                 .hsync_len      = 1,
 209                 .vsync_len      = 1,
 210                 .sync           = FB_SYNC_EXT,
 211                 .vmode          = FB_VMODE_NONINTERLACED
 212 } }, {
 213         .bus    = -1,
 214         .addr   = 3,
 215         .pixfmt = IPU_PIX_FMT_RGB24,
 216         .detect = detect_hdmi,
 217         .enable = do_enable_hdmi,
 218         .mode   = {
 219                 .name           = "HDMI",
 220                 .refresh        = 60,
 221                 .xres           = 1024,
 222                 .yres           = 768,
 223                 .pixclock       = 15385,
 224                 .left_margin    = 220,
 225                 .right_margin   = 40,
 226                 .upper_margin   = 21,
 227                 .lower_margin   = 7,
 228                 .hsync_len      = 60,
 229                 .vsync_len      = 10,
 230                 .sync           = FB_SYNC_EXT,
 231                 .vmode          = FB_VMODE_NONINTERLACED
 232 } } };
 233 size_t display_count = ARRAY_SIZE(displays);
 234
 235 static void enable_videopll(void)
 236 {
 237         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 238         s32 timeout = 100000;
 239
 240         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 241
 242         /* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
 243          *   |
 244          * PLL5
 245          *   |
 246          * CS2CDR[LDB_DI0_CLK_SEL]
 247          *   |
 248          *   +----> LDB_DI0_SERIAL_CLK_ROOT
 249          *   |
 250          *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
 251          */
 252
 253         clrsetbits_le32(&ccm->analog_pll_video,
 254                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 255                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 256                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 257                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 258
 259         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 260         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 261
 262         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 263
 264         while (timeout--)
 265                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 266                         break;
 267
 268         if (timeout < 0)
 269                 printf("Warning: video pll lock timeout!\n");
 270
 271         clrsetbits_le32(&ccm->analog_pll_video,
 272                         BM_ANADIG_PLL_VIDEO_BYPASS,
 273                         BM_ANADIG_PLL_VIDEO_ENABLE);
 274 }
 275
 276 static void setup_display_b850v3(void)
 277 {
 278         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 279         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 280
 281         enable_videopll();
 282
 283         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 284         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 285
 286         imx_setup_hdmi();
 287
 288         /* Set LDB_DI0 as clock source for IPU_DI0 */
 289         clrsetbits_le32(&mxc_ccm->chsccdr,
 290                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 291                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 292                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 293
 294         /* Turn on IPU LDB DI0 clocks */
 295         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 296
 297         enable_ipu_clock();
 298
 299         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 300                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 301                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 302                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 303                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 304                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 305                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 306                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 307                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 308                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 309                &iomux->gpr[2]);
 310
 311         clrbits_le32(&iomux->gpr[3],
 312                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 313                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 314                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 315 }
 316
 317 static void setup_display_bx50v3(void)
 318 {
 319         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 320         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 321
 322         enable_videopll();
 323
 324         /* When a reset/reboot is performed the display power needs to be turned
 325          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 326          * an additional 200ms here. Unfortunately we use external PMIC for
 327          * doing the reset, so can not differentiate between POR vs soft reset
 328          */
 329         mdelay(200);
 330
 331         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 332         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 333
 334         /* Set LDB_DI0 as clock source for IPU_DI0 */
 335         clrsetbits_le32(&mxc_ccm->chsccdr,
 336                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 337                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 338                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 339
 340         /* Turn on IPU LDB DI0 clocks */
 341         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 342
 343         enable_ipu_clock();
 344
 345         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 346                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 347                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 348                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 349                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 350                &iomux->gpr[2]);
 351
 352         clrsetbits_le32(&iomux->gpr[3],
 353                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 354                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 355                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 356
 357         /* backlights off until needed */
 358         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 359                                          ARRAY_SIZE(backlight_pads));
 360         gpio_request(LVDS_POWER_GP, "lvds_power");
 361         gpio_direction_input(LVDS_POWER_GP);
 362 }
 363 #endif /* CONFIG_VIDEO_IPUV3 */
 364
 365 /*
 366  * Do not overwrite the console
 367  * Use always serial for U-Boot console
 368  */
 369 int overwrite_console(void)
 370 {
 371         return 1;
 372 }
 373
 374 #define VPD_TYPE_INVALID 0x00
 375 #define VPD_BLOCK_NETWORK 0x20
 376 #define VPD_BLOCK_HWID 0x44
 377 #define VPD_PRODUCT_B850 1
 378 #define VPD_PRODUCT_B650 2
 379 #define VPD_PRODUCT_B450 3
 380 #define VPD_HAS_MAC1 0x1
 381 #define VPD_HAS_MAC2 0x2
 382 #define VPD_MAC_ADDRESS_LENGTH 6
 383
 384 struct vpd_cache {
 385         bool is_read;
 386         u8 product_id;
 387         u8 has;
 388         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 389         unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
 390 };
 391
 392 /*
 393  * Extracts MAC and product information from the VPD.
 394  */
 395 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
 396                         size_t size, u8 const *data)
 397 {
 398         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 399             size >= 1) {
 400                 vpd->product_id = data[0];
 401         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 402                    type != VPD_TYPE_INVALID) {
 403                 if (size >= 6) {
 404                         vpd->has |= VPD_HAS_MAC1;
 405                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 406                 }
 407                 if (size >= 12) {
 408                         vpd->has |= VPD_HAS_MAC2;
 409                         memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
 410                 }
 411         }
 412
 413         return 0;
 414 }
 415
 416 static void process_vpd(struct vpd_cache *vpd)
 417 {
 418         int fec_index = 0;
 419         int i210_index = -1;
 420
 421         if (!vpd->is_read) {
 422                 printf("VPD wasn't read");
 423                 return;
 424         }
 425
 426         if (vpd->has & VPD_HAS_MAC1)
 427                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 428
 429         env_set("ethact", "eth0");
 430
 431         switch (vpd->product_id) {
 432         case VPD_PRODUCT_B450:
 433                 env_set("confidx", "1");
 434                 i210_index = 1;
 435                 break;
 436         case VPD_PRODUCT_B650:
 437                 env_set("confidx", "2");
 438                 i210_index = 1;
 439                 break;
 440         case VPD_PRODUCT_B850:
 441                 env_set("confidx", "3");
 442                 i210_index = 2;
 443                 break;
 444         }
 445
 446         if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 447                 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 448 }
 449
 450 static iomux_v3_cfg_t const misc_pads[] = {
 451         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 452         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 453         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 454         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 455         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 456         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 457         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 458         MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 459 };
 460 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 461 #define WIFI_EN IMX_GPIO_NR(6, 14)
 462
 463 int board_early_init_f(void)
 464 {
 465         imx_iomux_v3_setup_multiple_pads(misc_pads,
 466                                          ARRAY_SIZE(misc_pads));
 467
 468         setup_iomux_uart();
 469
 470 #if defined(CONFIG_VIDEO_IPUV3)
 471         /* Set LDB clock to Video PLL */
 472         select_ldb_di_clock_source(MXC_PLL5_CLK);
 473 #endif
 474         return 0;
 475 }
 476
 477 static void set_confidx(const struct vpd_cache* vpd)
 478 {
 479         switch (vpd->product_id) {
 480         case VPD_PRODUCT_B450:
 481                 confidx = 1;
 482                 break;
 483         case VPD_PRODUCT_B650:
 484                 confidx = 2;
 485                 break;
 486         case VPD_PRODUCT_B850:
 487                 confidx = 3;
 488                 break;
 489         }
 490 }
 491
 492 int board_init(void)
 493 {
 494         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 495         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 496         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 497
 498         if (!read_vpd(&vpd, vpd_callback)) {
 499                 int ret, rescan;
 500
 501                 vpd.is_read = true;
 502                 set_confidx(&vpd);
 503
 504                 ret = fdtdec_resetup(&rescan);
 505                 if (!ret && rescan) {
 506                         dm_uninit();
 507                         dm_init_and_scan(false);
 508                 }
 509         }
 510
 511         gpio_request(SUS_S3_OUT, "sus_s3_out");
 512         gpio_direction_output(SUS_S3_OUT, 1);
 513
 514         gpio_request(WIFI_EN, "wifi_en");
 515         gpio_direction_output(WIFI_EN, 1);
 516
 517 #if defined(CONFIG_VIDEO_IPUV3)
 518         if (is_b850v3())
 519                 setup_display_b850v3();
 520         else
 521                 setup_display_bx50v3();
 522
 523         gpio_request(LVDS_BACKLIGHT_GP, "lvds_backlight");
 524         gpio_direction_input(LVDS_BACKLIGHT_GP);
 525 #endif
 526
 527         /* address of boot parameters */
 528         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 529
 530         return 0;
 531 }
 532
 533 #ifdef CONFIG_CMD_BMODE
 534 static const struct boot_mode board_boot_modes[] = {
 535         /* 4 bit bus width */
 536         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 537         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 538         {NULL,   0},
 539 };
 540 #endif
 541
 542 void pmic_init(void)
 543 {
 544 #define I2C_PMIC                0x2
 545 #define DA9063_I2C_ADDR         0x58
 546 #define DA9063_REG_BCORE2_CFG   0x9D
 547 #define DA9063_REG_BCORE1_CFG   0x9E
 548 #define DA9063_REG_BPRO_CFG     0x9F
 549 #define DA9063_REG_BIO_CFG      0xA0
 550 #define DA9063_REG_BMEM_CFG     0xA1
 551 #define DA9063_REG_BPERI_CFG    0xA2
 552 #define DA9063_BUCK_MODE_MASK   0xC0
 553 #define DA9063_BUCK_MODE_MANUAL 0x00
 554 #define DA9063_BUCK_MODE_SLEEP  0x40
 555 #define DA9063_BUCK_MODE_SYNC   0x80
 556 #define DA9063_BUCK_MODE_AUTO   0xC0
 557
 558         uchar val;
 559
 560         i2c_set_bus_num(I2C_PMIC);
 561
 562         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 563         val &= ~DA9063_BUCK_MODE_MASK;
 564         val |= DA9063_BUCK_MODE_SYNC;
 565         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 566
 567         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 568         val &= ~DA9063_BUCK_MODE_MASK;
 569         val |= DA9063_BUCK_MODE_SYNC;
 570         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 571
 572         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 573         val &= ~DA9063_BUCK_MODE_MASK;
 574         val |= DA9063_BUCK_MODE_SYNC;
 575         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 576
 577         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 578         val &= ~DA9063_BUCK_MODE_MASK;
 579         val |= DA9063_BUCK_MODE_SYNC;
 580         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 581
 582         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 583         val &= ~DA9063_BUCK_MODE_MASK;
 584         val |= DA9063_BUCK_MODE_SYNC;
 585         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 586
 587         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 588         val &= ~DA9063_BUCK_MODE_MASK;
 589         val |= DA9063_BUCK_MODE_SYNC;
 590         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 591 }
 592
 593 int board_late_init(void)
 594 {
 595         process_vpd(&vpd);
 596
 597 #ifdef CONFIG_CMD_BMODE
 598         add_board_boot_modes(board_boot_modes);
 599 #endif
 600
 601         if (is_b850v3())
 602                 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
 603         else
 604                 env_set("videoargs", "video=LVDS-1:1024x768@65");
 605
 606         /* board specific pmic init */
 607         pmic_init();
 608
 609         check_time();
 610
 611         pci_init();
 612
 613         return 0;
 614 }
 615
 616 /*
 617  * Removes the 'eth[0-9]*addr' environment variable with the given index
 618  *
 619  * @param index [in] the index of the eth_device whose variable is to be removed
 620  */
 621 static void remove_ethaddr_env_var(int index)
 622 {
 623         char env_var_name[9];
 624
 625         sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
 626         env_set(env_var_name, NULL);
 627 }
 628
 629 int last_stage_init(void)
 630 {
 631         int i;
 632
 633         /*
 634          * Remove first three ethaddr which may have been created by
 635          * function process_vpd().
 636          */
 637         for (i = 0; i < 3; ++i)
 638                 remove_ethaddr_env_var(i);
 639
 640         return 0;
 641 }
 642
 643 int checkboard(void)
 644 {
 645         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 646         return 0;
 647 }
 648
 649 #ifdef CONFIG_OF_BOARD_SETUP
 650 int ft_board_setup(void *blob, bd_t *bd)
 651 {
 652         char *rtc_status = env_get("rtc_status");
 653
 654         fdt_setprop(blob, 0, "ge,boot-ver", version_string,
 655                     strlen(version_string) + 1);
 656
 657         fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
 658                     strlen(rtc_status) + 1);
 659         return 0;
 660 }
 661 #endif
 662
 663 static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 664 {
 665 #if CONFIG_IS_ENABLED(DM_VIDEO)
 666         int ret;
 667         struct udevice *dev;
 668
 669 #ifdef CONFIG_VIDEO_IPUV3
 670         if (!is_b850v3()) {
 671                 gpio_direction_output(LVDS_POWER_GP, 1);
 672
 673                 /* We need at least 200ms between power on and backlight on
 674                  * as per specifications from CHI MEI
 675                  */
 676                 mdelay(250);
 677
 678                 /* enable backlight PWM 1 */
 679                 pwm_init(0, 0, 0);
 680
 681                 /* duty cycle 5000000ns, period: 5000000ns */
 682                 pwm_config(0, 5000000, 5000000);
 683
 684                 /* Backlight Power */
 685                 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 686
 687                 pwm_enable(0);
 688         }
 689 #endif
 690
 691         /* Probe, to find a video device to be used to show a message on
 692          * the vidconsole.
 693          */
 694         ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
 695         if (ret)
 696                 return ret;
 697 #endif
 698
 699         return 0;
 700 }
 701
 702 U_BOOT_CMD(
 703        bx50_backlight_enable, 1,      1,      do_backlight_enable,
 704        "enable Bx50 backlight",
 705        ""
 706 );
 707
 708 int board_fit_config_name_match(const char *name)
 709 {
 710         if (!vpd.is_read)
 711                 return strcmp(name, "imx6q-bx50v3");
 712
 713         switch (vpd.product_id) {
 714         case VPD_PRODUCT_B450:
 715                 return strcmp(name, "imx6q-b450v3");
 716         case VPD_PRODUCT_B650:
 717                 return strcmp(name, "imx6q-b650v3");
 718         case VPD_PRODUCT_B850:
 719                 return strcmp(name, "imx6q-b850v3");
 720         default:
 721                 return -1;
 722         }
 723 }
 724
 725 int embedded_dtb_select(void)
 726 {
 727         vpd.is_read = false;
 728         return fdtdec_setup();
 729 }