board/ge/bx50v3/bx50v3.c

   1 /*
   2  * Copyright 2015 Timesys Corporation
   3  * Copyright 2015 General Electric Company
   4  * Copyright 2012 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <linux/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-imx/mxc_i2c.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/mach-imx/video.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <miiphy.h>
  22 #include <net.h>
  23 #include <netdev.h>
  24 #include <asm/arch/mxc_hdmi.h>
  25 #include <asm/arch/crm_regs.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <i2c.h>
  29 #include <input.h>
  30 #include <pwm.h>
  31 #include <stdlib.h>
  32 #include "../common/vpd_reader.h"
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #ifndef CONFIG_SYS_I2C_EEPROM_ADDR
  36 # define CONFIG_SYS_I2C_EEPROM_ADDR     0x50
  37 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  38 #endif
  39
  40 #ifndef CONFIG_SYS_I2C_EEPROM_BUS
  41 #define CONFIG_SYS_I2C_EEPROM_BUS       4
  42 #endif
  43
  44 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  46         PAD_CTL_HYS)
  47
  48 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  49         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  50         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  51
  52 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  53         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  54         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  55
  56 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  57         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  58
  59 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  60         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  61
  62 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  63         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  64
  65 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  66                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  67
  68 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  69         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  70         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  71
  72 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  73
  74 int dram_init(void)
  75 {
  76         gd->ram_size = imx_ddr_size();
  77
  78         return 0;
  79 }
  80
  81 static iomux_v3_cfg_t const uart3_pads[] = {
  82         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  83         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  84         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  85         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  86 };
  87
  88 static iomux_v3_cfg_t const uart4_pads[] = {
  89         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  90         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  91 };
  92
  93 static iomux_v3_cfg_t const enet_pads[] = {
  94         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  95         MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  96         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  97         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  98         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  99         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 100         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 101         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 102         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 103         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 104         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 105         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 106         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 107         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 108         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 109         /* AR8033 PHY Reset */
 110         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 111 };
 112
 113 static void setup_iomux_enet(void)
 114 {
 115         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 116
 117         /* Reset AR8033 PHY */
 118         gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
 119         mdelay(10);
 120         gpio_set_value(IMX_GPIO_NR(1, 28), 1);
 121         mdelay(1);
 122 }
 123
 124 static iomux_v3_cfg_t const usdhc2_pads[] = {
 125         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 126         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 127         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(NO_PAD_CTRL),
 132 };
 133
 134 static iomux_v3_cfg_t const usdhc3_pads[] = {
 135         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146 };
 147
 148 static iomux_v3_cfg_t const usdhc4_pads[] = {
 149         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 150         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 152         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 153         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 154         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 155         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 156         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 157         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 158         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 159         MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 160         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 161 };
 162
 163 static iomux_v3_cfg_t const ecspi1_pads[] = {
 164         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 165         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 166         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 167         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 168 };
 169
 170 static struct i2c_pads_info i2c_pad_info1 = {
 171         .scl = {
 172                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
 173                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
 174                 .gp = IMX_GPIO_NR(5, 27)
 175         },
 176         .sda = {
 177                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
 178                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
 179                 .gp = IMX_GPIO_NR(5, 26)
 180         }
 181 };
 182
 183 static struct i2c_pads_info i2c_pad_info2 = {
 184         .scl = {
 185                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 186                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 187                 .gp = IMX_GPIO_NR(4, 12)
 188         },
 189         .sda = {
 190                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 191                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 192                 .gp = IMX_GPIO_NR(4, 13)
 193         }
 194 };
 195
 196 static struct i2c_pads_info i2c_pad_info3 = {
 197         .scl = {
 198                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
 199                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
 200                 .gp = IMX_GPIO_NR(1, 3)
 201         },
 202         .sda = {
 203                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 204                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 205                 .gp = IMX_GPIO_NR(1, 6)
 206         }
 207 };
 208
 209 #ifdef CONFIG_MXC_SPI
 210 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 211 {
 212         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
 213 }
 214
 215 static void setup_spi(void)
 216 {
 217         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 218 }
 219 #endif
 220
 221 static iomux_v3_cfg_t const pcie_pads[] = {
 222         MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 223         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 224 };
 225
 226 static void setup_pcie(void)
 227 {
 228         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 229 }
 230
 231 static void setup_iomux_uart(void)
 232 {
 233         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 234         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 235 }
 236
 237 #ifdef CONFIG_FSL_ESDHC
 238 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 239         {USDHC2_BASE_ADDR},
 240         {USDHC3_BASE_ADDR},
 241         {USDHC4_BASE_ADDR},
 242 };
 243
 244 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 245 #define USDHC4_CD_GPIO  IMX_GPIO_NR(6, 11)
 246
 247 int board_mmc_getcd(struct mmc *mmc)
 248 {
 249         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 250         int ret = 0;
 251
 252         switch (cfg->esdhc_base) {
 253         case USDHC2_BASE_ADDR:
 254                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 255                 break;
 256         case USDHC3_BASE_ADDR:
 257                 ret = 1; /* eMMC is always present */
 258                 break;
 259         case USDHC4_BASE_ADDR:
 260                 ret = !gpio_get_value(USDHC4_CD_GPIO);
 261                 break;
 262         }
 263
 264         return ret;
 265 }
 266
 267 int board_mmc_init(bd_t *bis)
 268 {
 269         int ret;
 270         int i;
 271
 272         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 273                 switch (i) {
 274                 case 0:
 275                         imx_iomux_v3_setup_multiple_pads(
 276                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 277                         gpio_direction_input(USDHC2_CD_GPIO);
 278                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 279                         break;
 280                 case 1:
 281                         imx_iomux_v3_setup_multiple_pads(
 282                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 283                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 284                         break;
 285                 case 2:
 286                         imx_iomux_v3_setup_multiple_pads(
 287                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 288                         gpio_direction_input(USDHC4_CD_GPIO);
 289                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 290                         break;
 291                 default:
 292                         printf("Warning: you configured more USDHC controllers\n"
 293                                "(%d) then supported by the board (%d)\n",
 294                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 295                         return -EINVAL;
 296                 }
 297
 298                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 299                 if (ret)
 300                         return ret;
 301         }
 302
 303         return 0;
 304 }
 305 #endif
 306
 307 static int mx6_rgmii_rework(struct phy_device *phydev)
 308 {
 309         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
 310         /* set device address 0x7 */
 311         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 312         /* offset 0x8016: CLK_25M Clock Select */
 313         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 314         /* enable register write, no post increment, address 0x7 */
 315         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 316         /* set to 125 MHz from local PLL source */
 317         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 318
 319         /* rgmii tx clock delay enable */
 320         /* set debug port address: SerDes Test and System Mode Control */
 321         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 322         /* enable rgmii tx clock delay */
 323         /* set the reserved bits to avoid board specific voltage peak issue*/
 324         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 325
 326         return 0;
 327 }
 328
 329 int board_phy_config(struct phy_device *phydev)
 330 {
 331         mx6_rgmii_rework(phydev);
 332
 333         if (phydev->drv->config)
 334                 phydev->drv->config(phydev);
 335
 336         return 0;
 337 }
 338
 339 #if defined(CONFIG_VIDEO_IPUV3)
 340 static iomux_v3_cfg_t const backlight_pads[] = {
 341         /* Power for LVDS Display */
 342         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 343 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 344         /* Backlight enable for LVDS display */
 345         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 346 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 347         /* backlight PWM brightness control */
 348         MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 349 };
 350
 351 static void do_enable_hdmi(struct display_info_t const *dev)
 352 {
 353         imx_enable_hdmi_phy();
 354 }
 355
 356 int board_cfb_skip(void)
 357 {
 358         gpio_direction_output(LVDS_POWER_GP, 1);
 359
 360         return 0;
 361 }
 362
 363 static int detect_baseboard(struct display_info_t const *dev)
 364 {
 365         if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
 366             IS_ENABLED(CONFIG_TARGET_GE_B650V3))
 367                 return 1;
 368
 369         return 0;
 370 }
 371
 372 struct display_info_t const displays[] = {{
 373         .bus    = -1,
 374         .addr   = -1,
 375         .pixfmt = IPU_PIX_FMT_RGB24,
 376         .detect = detect_baseboard,
 377         .enable = NULL,
 378         .mode   = {
 379                 .name           = "G121X1-L03",
 380                 .refresh        = 60,
 381                 .xres           = 1024,
 382                 .yres           = 768,
 383                 .pixclock       = 15385,
 384                 .left_margin    = 20,
 385                 .right_margin   = 300,
 386                 .upper_margin   = 30,
 387                 .lower_margin   = 8,
 388                 .hsync_len      = 1,
 389                 .vsync_len      = 1,
 390                 .sync           = FB_SYNC_EXT,
 391                 .vmode          = FB_VMODE_NONINTERLACED
 392 } }, {
 393         .bus    = -1,
 394         .addr   = 3,
 395         .pixfmt = IPU_PIX_FMT_RGB24,
 396         .detect = detect_hdmi,
 397         .enable = do_enable_hdmi,
 398         .mode   = {
 399                 .name           = "HDMI",
 400                 .refresh        = 60,
 401                 .xres           = 1024,
 402                 .yres           = 768,
 403                 .pixclock       = 15385,
 404                 .left_margin    = 220,
 405                 .right_margin   = 40,
 406                 .upper_margin   = 21,
 407                 .lower_margin   = 7,
 408                 .hsync_len      = 60,
 409                 .vsync_len      = 10,
 410                 .sync           = FB_SYNC_EXT,
 411                 .vmode          = FB_VMODE_NONINTERLACED
 412 } } };
 413 size_t display_count = ARRAY_SIZE(displays);
 414
 415 static void enable_videopll(void)
 416 {
 417         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 418         s32 timeout = 100000;
 419
 420         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 421
 422         /* set video pll to 910MHz (24MHz * (37+11/12))
 423         * video pll post div to 910/4 = 227.5MHz
 424         */
 425         clrsetbits_le32(&ccm->analog_pll_video,
 426                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 427                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 428                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 429                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0));
 430
 431         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 432         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 433
 434         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 435
 436         while (timeout--)
 437                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 438                         break;
 439
 440         if (timeout < 0)
 441                 printf("Warning: video pll lock timeout!\n");
 442
 443         clrsetbits_le32(&ccm->analog_pll_video,
 444                         BM_ANADIG_PLL_VIDEO_BYPASS,
 445                         BM_ANADIG_PLL_VIDEO_ENABLE);
 446 }
 447
 448 static void setup_display_b850v3(void)
 449 {
 450         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 451         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 452
 453         enable_videopll();
 454
 455         /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
 456         clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 457
 458         imx_setup_hdmi();
 459
 460         /* Set LDB_DI0 as clock source for IPU_DI0 */
 461         clrsetbits_le32(&mxc_ccm->chsccdr,
 462                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 463                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 464                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 465
 466         /* Turn on IPU LDB DI0 clocks */
 467         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 468
 469         enable_ipu_clock();
 470
 471         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 472                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 473                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 474                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 475                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 476                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 477                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 478                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 479                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 480                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 481                &iomux->gpr[2]);
 482
 483         clrbits_le32(&iomux->gpr[3],
 484                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 485                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 486                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 487 }
 488
 489 static void setup_display_bx50v3(void)
 490 {
 491         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 492         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 493
 494         /* When a reset/reboot is performed the display power needs to be turned
 495          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 496          * an additional 200ms here. Unfortunately we use external PMIC for
 497          * doing the reset, so can not differentiate between POR vs soft reset
 498          */
 499         mdelay(200);
 500
 501         /* IPU1 DI0 clock is 480/7 = 68.5 MHz */
 502         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 503
 504         /* Set LDB_DI0 as clock source for IPU_DI0 */
 505         clrsetbits_le32(&mxc_ccm->chsccdr,
 506                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 507                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 508                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 509
 510         /* Turn on IPU LDB DI0 clocks */
 511         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 512
 513         enable_ipu_clock();
 514
 515         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 516                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 517                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 518                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 519                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 520                &iomux->gpr[2]);
 521
 522         clrsetbits_le32(&iomux->gpr[3],
 523                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 524                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 525                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 526
 527         /* backlights off until needed */
 528         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 529                                          ARRAY_SIZE(backlight_pads));
 530         gpio_direction_input(LVDS_POWER_GP);
 531         gpio_direction_input(LVDS_BACKLIGHT_GP);
 532 }
 533 #endif /* CONFIG_VIDEO_IPUV3 */
 534
 535 /*
 536  * Do not overwrite the console
 537  * Use always serial for U-Boot console
 538  */
 539 int overwrite_console(void)
 540 {
 541         return 1;
 542 }
 543
 544 #define VPD_TYPE_INVALID 0x00
 545 #define VPD_BLOCK_NETWORK 0x20
 546 #define VPD_BLOCK_HWID 0x44
 547 #define VPD_PRODUCT_B850 1
 548 #define VPD_PRODUCT_B650 2
 549 #define VPD_PRODUCT_B450 3
 550 #define VPD_HAS_MAC1 0x1
 551 #define VPD_MAC_ADDRESS_LENGTH 6
 552
 553 struct vpd_cache {
 554         u8 product_id;
 555         u8 has;
 556         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 557 };
 558
 559 /*
 560  * Extracts MAC and product information from the VPD.
 561  */
 562 static int vpd_callback(void *userdata, u8 id, u8 version, u8 type,
 563                         size_t size, u8 const *data)
 564 {
 565         struct vpd_cache *vpd = (struct vpd_cache *)userdata;
 566
 567         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 568             size >= 1) {
 569                 vpd->product_id = data[0];
 570         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 571                    type != VPD_TYPE_INVALID) {
 572                 if (size >= 6) {
 573                         vpd->has |= VPD_HAS_MAC1;
 574                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 575                 }
 576         }
 577
 578         return 0;
 579 }
 580
 581 static void process_vpd(struct vpd_cache *vpd)
 582 {
 583         int fec_index = -1;
 584
 585         switch (vpd->product_id) {
 586         case VPD_PRODUCT_B450:
 587                 /* fall thru */
 588         case VPD_PRODUCT_B650:
 589                 fec_index = 1;
 590                 break;
 591         case VPD_PRODUCT_B850:
 592                 fec_index = 2;
 593                 break;
 594         }
 595
 596         if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
 597                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 598 }
 599
 600 static int read_vpd(uint eeprom_bus)
 601 {
 602         struct vpd_cache vpd;
 603         int res;
 604         int size = 1024;
 605         uint8_t *data;
 606         unsigned int current_i2c_bus = i2c_get_bus_num();
 607
 608         res = i2c_set_bus_num(eeprom_bus);
 609         if (res < 0)
 610                 return res;
 611
 612         data = (uint8_t *)malloc(size);
 613         if (!data)
 614                 return -ENOMEM;
 615
 616         res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
 617                         CONFIG_SYS_I2C_EEPROM_ADDR_LEN, data, size);
 618
 619         if (res == 0) {
 620                 memset(&vpd, 0, sizeof(vpd));
 621                 vpd_reader(size, data, &vpd, vpd_callback);
 622                 process_vpd(&vpd);
 623         }
 624
 625         free(data);
 626
 627         i2c_set_bus_num(current_i2c_bus);
 628         return res;
 629 }
 630
 631 int board_eth_init(bd_t *bis)
 632 {
 633         setup_iomux_enet();
 634         setup_pcie();
 635
 636         return cpu_eth_init(bis);
 637 }
 638
 639 static iomux_v3_cfg_t const misc_pads[] = {
 640         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 641         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 642         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 643         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 644         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 645         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 646         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 647 };
 648 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 649 #define WIFI_EN IMX_GPIO_NR(6, 14)
 650
 651 int board_early_init_f(void)
 652 {
 653         imx_iomux_v3_setup_multiple_pads(misc_pads,
 654                                          ARRAY_SIZE(misc_pads));
 655
 656         setup_iomux_uart();
 657
 658 #if defined(CONFIG_VIDEO_IPUV3)
 659         if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
 660                 /* Set LDB clock to Video PLL */
 661                 select_ldb_di_clock_source(MXC_PLL5_CLK);
 662         else
 663                 /* Set LDB clock to USB PLL */
 664                 select_ldb_di_clock_source(MXC_PLL3_SW_CLK);
 665 #endif
 666         return 0;
 667 }
 668
 669 int board_init(void)
 670 {
 671         gpio_direction_output(SUS_S3_OUT, 1);
 672         gpio_direction_output(WIFI_EN, 1);
 673 #if defined(CONFIG_VIDEO_IPUV3)
 674         if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
 675                 setup_display_b850v3();
 676         else
 677                 setup_display_bx50v3();
 678 #endif
 679         /* address of boot parameters */
 680         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 681
 682 #ifdef CONFIG_MXC_SPI
 683         setup_spi();
 684 #endif
 685         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 686         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 687         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 688
 689         return 0;
 690 }
 691
 692 #ifdef CONFIG_CMD_BMODE
 693 static const struct boot_mode board_boot_modes[] = {
 694         /* 4 bit bus width */
 695         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 696         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 697         {NULL,   0},
 698 };
 699 #endif
 700
 701 void pmic_init(void)
 702 {
 703 #define I2C_PMIC                0x2
 704 #define DA9063_I2C_ADDR         0x58
 705 #define DA9063_REG_BCORE2_CFG   0x9D
 706 #define DA9063_REG_BCORE1_CFG   0x9E
 707 #define DA9063_REG_BPRO_CFG     0x9F
 708 #define DA9063_REG_BIO_CFG      0xA0
 709 #define DA9063_REG_BMEM_CFG     0xA1
 710 #define DA9063_REG_BPERI_CFG    0xA2
 711 #define DA9063_BUCK_MODE_MASK   0xC0
 712 #define DA9063_BUCK_MODE_MANUAL 0x00
 713 #define DA9063_BUCK_MODE_SLEEP  0x40
 714 #define DA9063_BUCK_MODE_SYNC   0x80
 715 #define DA9063_BUCK_MODE_AUTO   0xC0
 716
 717         uchar val;
 718
 719         i2c_set_bus_num(I2C_PMIC);
 720
 721         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 722         val &= ~DA9063_BUCK_MODE_MASK;
 723         val |= DA9063_BUCK_MODE_SYNC;
 724         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 725
 726         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 727         val &= ~DA9063_BUCK_MODE_MASK;
 728         val |= DA9063_BUCK_MODE_SYNC;
 729         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 730
 731         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 732         val &= ~DA9063_BUCK_MODE_MASK;
 733         val |= DA9063_BUCK_MODE_SYNC;
 734         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 735
 736         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 737         val &= ~DA9063_BUCK_MODE_MASK;
 738         val |= DA9063_BUCK_MODE_SYNC;
 739         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 740
 741         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 742         val &= ~DA9063_BUCK_MODE_MASK;
 743         val |= DA9063_BUCK_MODE_SYNC;
 744         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 745
 746         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 747         val &= ~DA9063_BUCK_MODE_MASK;
 748         val |= DA9063_BUCK_MODE_SYNC;
 749         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 750 }
 751
 752 int board_late_init(void)
 753 {
 754         read_vpd(CONFIG_SYS_I2C_EEPROM_BUS);
 755
 756 #ifdef CONFIG_CMD_BMODE
 757         add_board_boot_modes(board_boot_modes);
 758 #endif
 759
 760 #ifdef CONFIG_VIDEO_IPUV3
 761         /* We need at least 200ms between power on and backlight on
 762          * as per specifications from CHI MEI */
 763         mdelay(250);
 764
 765         /* enable backlight PWM 1 */
 766         pwm_init(0, 0, 0);
 767
 768         /* duty cycle 5000000ns, period: 5000000ns */
 769         pwm_config(0, 5000000, 5000000);
 770
 771         /* Backlight Power */
 772         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 773
 774         pwm_enable(0);
 775 #endif
 776
 777         /* board specific pmic init */
 778         pmic_init();
 779
 780         return 0;
 781 }
 782
 783 int last_stage_init(void)
 784 {
 785         env_set("ethaddr", NULL);
 786
 787         return 0;
 788 }
 789
 790 int checkboard(void)
 791 {
 792         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 793         return 0;
 794 }