board/ge/bx50v3/bx50v3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Timesys Corporation
   4  * Copyright 2015 General Electric Company
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <init.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <env.h>
  14 #include <linux/errno.h>
  15 #include <linux/libfdt.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/boot_mode.h>
  19 #include <asm/mach-imx/video.h>
  20 #include <mmc.h>
  21 #include <fsl_esdhc_imx.h>
  22 #include <miiphy.h>
  23 #include <net.h>
  24 #include <netdev.h>
  25 #include <asm/arch/mxc_hdmi.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/io.h>
  28 #include <asm/arch/sys_proto.h>
  29 #include <power/regulator.h>
  30 #include <power/da9063_pmic.h>
  31 #include <input.h>
  32 #include <pwm.h>
  33 #include <version.h>
  34 #include <stdlib.h>
  35 #include <dm/root.h>
  36 #include "../common/ge_common.h"
  37 #include "../common/vpd_reader.h"
  38 #include "../../../drivers/net/e1000.h"
  39 #include <pci.h>
  40 #include <panel.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 static int confidx;  /* Default to generic. */
  45 static struct vpd_cache vpd;
  46
  47 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  48         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  49         PAD_CTL_HYS)
  50
  51 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  52         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  53
  54 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  55         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  56
  57 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  58         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  59
  60 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  61         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  62         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  63
  64 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  65
  66 int dram_init(void)
  67 {
  68         gd->ram_size = imx_ddr_size();
  69
  70         return 0;
  71 }
  72
  73 static int mx6_rgmii_rework(struct phy_device *phydev)
  74 {
  75         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
  76         /* set device address 0x7 */
  77         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  78         /* offset 0x8016: CLK_25M Clock Select */
  79         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  80         /* enable register write, no post increment, address 0x7 */
  81         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  82         /* set to 125 MHz from local PLL source */
  83         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
  84
  85         /* rgmii tx clock delay enable */
  86         /* set debug port address: SerDes Test and System Mode Control */
  87         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  88         /* enable rgmii tx clock delay */
  89         /* set the reserved bits to avoid board specific voltage peak issue*/
  90         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
  91
  92         return 0;
  93 }
  94
  95 int board_phy_config(struct phy_device *phydev)
  96 {
  97         mx6_rgmii_rework(phydev);
  98
  99         if (phydev->drv->config)
 100                 phydev->drv->config(phydev);
 101
 102         return 0;
 103 }
 104
 105 #if defined(CONFIG_VIDEO_IPUV3)
 106 static void do_enable_backlight(struct display_info_t const *dev)
 107 {
 108         struct udevice *panel;
 109         int ret;
 110
 111         ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
 112         if (ret) {
 113                 printf("Could not find panel: %d\n", ret);
 114                 return;
 115         }
 116
 117         panel_set_backlight(panel, 100);
 118         panel_enable_backlight(panel);
 119 }
 120
 121 static void do_enable_hdmi(struct display_info_t const *dev)
 122 {
 123         imx_enable_hdmi_phy();
 124 }
 125
 126 static int is_b850v3(void)
 127 {
 128         return confidx == 3;
 129 }
 130
 131 static int detect_lcd(struct display_info_t const *dev)
 132 {
 133         return !is_b850v3();
 134 }
 135
 136 struct display_info_t const displays[] = {{
 137         .bus    = -1,
 138         .addr   = -1,
 139         .pixfmt = IPU_PIX_FMT_RGB24,
 140         .detect = detect_lcd,
 141         .enable = do_enable_backlight,
 142         .mode   = {
 143                 .name           = "G121X1-L03",
 144                 .refresh        = 60,
 145                 .xres           = 1024,
 146                 .yres           = 768,
 147                 .pixclock       = 15385,
 148                 .left_margin    = 20,
 149                 .right_margin   = 300,
 150                 .upper_margin   = 30,
 151                 .lower_margin   = 8,
 152                 .hsync_len      = 1,
 153                 .vsync_len      = 1,
 154                 .sync           = FB_SYNC_EXT,
 155                 .vmode          = FB_VMODE_NONINTERLACED
 156 } }, {
 157         .bus    = -1,
 158         .addr   = 3,
 159         .pixfmt = IPU_PIX_FMT_RGB24,
 160         .detect = detect_hdmi,
 161         .enable = do_enable_hdmi,
 162         .mode   = {
 163                 .name           = "HDMI",
 164                 .refresh        = 60,
 165                 .xres           = 1024,
 166                 .yres           = 768,
 167                 .pixclock       = 15385,
 168                 .left_margin    = 220,
 169                 .right_margin   = 40,
 170                 .upper_margin   = 21,
 171                 .lower_margin   = 7,
 172                 .hsync_len      = 60,
 173                 .vsync_len      = 10,
 174                 .sync           = FB_SYNC_EXT,
 175                 .vmode          = FB_VMODE_NONINTERLACED
 176 } } };
 177 size_t display_count = ARRAY_SIZE(displays);
 178
 179 static void enable_videopll(void)
 180 {
 181         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 182         s32 timeout = 100000;
 183
 184         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 185
 186         /* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
 187          *   |
 188          * PLL5
 189          *   |
 190          * CS2CDR[LDB_DI0_CLK_SEL]
 191          *   |
 192          *   +----> LDB_DI0_SERIAL_CLK_ROOT
 193          *   |
 194          *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
 195          */
 196
 197         clrsetbits_le32(&ccm->analog_pll_video,
 198                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 199                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 200                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 201                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 202
 203         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 204         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 205
 206         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 207
 208         while (timeout--)
 209                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 210                         break;
 211
 212         if (timeout < 0)
 213                 printf("Warning: video pll lock timeout!\n");
 214
 215         clrsetbits_le32(&ccm->analog_pll_video,
 216                         BM_ANADIG_PLL_VIDEO_BYPASS,
 217                         BM_ANADIG_PLL_VIDEO_ENABLE);
 218 }
 219
 220 static void setup_display_b850v3(void)
 221 {
 222         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 223         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 224
 225         enable_videopll();
 226
 227         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 228         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 229
 230         imx_setup_hdmi();
 231
 232         /* Set LDB_DI0 as clock source for IPU_DI0 */
 233         clrsetbits_le32(&mxc_ccm->chsccdr,
 234                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 235                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 236                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 237
 238         /* Turn on IPU LDB DI0 clocks */
 239         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 240
 241         enable_ipu_clock();
 242
 243         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 244                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 245                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 246                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 247                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 248                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 249                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 250                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 251                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 252                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 253                &iomux->gpr[2]);
 254
 255         clrbits_le32(&iomux->gpr[3],
 256                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 257                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 258                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 259 }
 260
 261 static void setup_display_bx50v3(void)
 262 {
 263         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 264         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 265
 266         enable_videopll();
 267
 268         /* When a reset/reboot is performed the display power needs to be turned
 269          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 270          * an additional 200ms here. Unfortunately we use external PMIC for
 271          * doing the reset, so can not differentiate between POR vs soft reset
 272          */
 273         mdelay(200);
 274
 275         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 276         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 277
 278         /* Set LDB_DI0 as clock source for IPU_DI0 */
 279         clrsetbits_le32(&mxc_ccm->chsccdr,
 280                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 281                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 282                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 283
 284         /* Turn on IPU LDB DI0 clocks */
 285         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 286
 287         enable_ipu_clock();
 288
 289         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 290                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 291                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 292                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 293                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 294                &iomux->gpr[2]);
 295
 296         clrsetbits_le32(&iomux->gpr[3],
 297                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 298                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 299                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 300 }
 301 #endif /* CONFIG_VIDEO_IPUV3 */
 302
 303 /*
 304  * Do not overwrite the console
 305  * Use always serial for U-Boot console
 306  */
 307 int overwrite_console(void)
 308 {
 309         return 1;
 310 }
 311
 312 #define VPD_TYPE_INVALID 0x00
 313 #define VPD_BLOCK_NETWORK 0x20
 314 #define VPD_BLOCK_HWID 0x44
 315 #define VPD_PRODUCT_B850 1
 316 #define VPD_PRODUCT_B650 2
 317 #define VPD_PRODUCT_B450 3
 318 #define VPD_HAS_MAC1 0x1
 319 #define VPD_HAS_MAC2 0x2
 320 #define VPD_MAC_ADDRESS_LENGTH 6
 321
 322 struct vpd_cache {
 323         bool is_read;
 324         u8 product_id;
 325         u8 has;
 326         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 327         unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
 328 };
 329
 330 /*
 331  * Extracts MAC and product information from the VPD.
 332  */
 333 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
 334                         size_t size, u8 const *data)
 335 {
 336         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 337             size >= 1) {
 338                 vpd->product_id = data[0];
 339         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 340                    type != VPD_TYPE_INVALID) {
 341                 if (size >= 6) {
 342                         vpd->has |= VPD_HAS_MAC1;
 343                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 344                 }
 345                 if (size >= 12) {
 346                         vpd->has |= VPD_HAS_MAC2;
 347                         memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
 348                 }
 349         }
 350
 351         return 0;
 352 }
 353
 354 static void process_vpd(struct vpd_cache *vpd)
 355 {
 356         int fec_index = 0;
 357         int i210_index = -1;
 358
 359         if (!vpd->is_read) {
 360                 printf("VPD wasn't read");
 361                 return;
 362         }
 363
 364         if (vpd->has & VPD_HAS_MAC1)
 365                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 366
 367         env_set("ethact", "eth0");
 368
 369         switch (vpd->product_id) {
 370         case VPD_PRODUCT_B450:
 371                 env_set("confidx", "1");
 372                 i210_index = 1;
 373                 break;
 374         case VPD_PRODUCT_B650:
 375                 env_set("confidx", "2");
 376                 i210_index = 1;
 377                 break;
 378         case VPD_PRODUCT_B850:
 379                 env_set("confidx", "3");
 380                 i210_index = 2;
 381                 break;
 382         }
 383
 384         if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 385                 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 386 }
 387
 388 static iomux_v3_cfg_t const misc_pads[] = {
 389         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 390         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 391         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 392         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 393         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 394         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 395         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 396         MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 397 };
 398 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 399 #define WIFI_EN IMX_GPIO_NR(6, 14)
 400
 401 int board_early_init_f(void)
 402 {
 403         imx_iomux_v3_setup_multiple_pads(misc_pads,
 404                                          ARRAY_SIZE(misc_pads));
 405
 406 #if defined(CONFIG_VIDEO_IPUV3)
 407         /* Set LDB clock to Video PLL */
 408         select_ldb_di_clock_source(MXC_PLL5_CLK);
 409 #endif
 410         return 0;
 411 }
 412
 413 static void set_confidx(const struct vpd_cache* vpd)
 414 {
 415         switch (vpd->product_id) {
 416         case VPD_PRODUCT_B450:
 417                 confidx = 1;
 418                 break;
 419         case VPD_PRODUCT_B650:
 420                 confidx = 2;
 421                 break;
 422         case VPD_PRODUCT_B850:
 423                 confidx = 3;
 424                 break;
 425         }
 426 }
 427
 428 int board_init(void)
 429 {
 430         if (!read_vpd(&vpd, vpd_callback)) {
 431                 int ret, rescan;
 432
 433                 vpd.is_read = true;
 434                 set_confidx(&vpd);
 435
 436                 ret = fdtdec_resetup(&rescan);
 437                 if (!ret && rescan) {
 438                         dm_uninit();
 439                         dm_init_and_scan(false);
 440                 }
 441         }
 442
 443         gpio_request(SUS_S3_OUT, "sus_s3_out");
 444         gpio_direction_output(SUS_S3_OUT, 1);
 445
 446         gpio_request(WIFI_EN, "wifi_en");
 447         gpio_direction_output(WIFI_EN, 1);
 448
 449 #if defined(CONFIG_VIDEO_IPUV3)
 450         if (is_b850v3())
 451                 setup_display_b850v3();
 452         else
 453                 setup_display_bx50v3();
 454 #endif
 455
 456         /* address of boot parameters */
 457         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 458
 459         return 0;
 460 }
 461
 462 #ifdef CONFIG_CMD_BMODE
 463 static const struct boot_mode board_boot_modes[] = {
 464         /* 4 bit bus width */
 465         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 466         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 467         {NULL,   0},
 468 };
 469 #endif
 470
 471 void pmic_init(void)
 472 {
 473         struct udevice *reg;
 474         int ret, i;
 475         static const char * const bucks[] = {
 476                 "bcore1",
 477                 "bcore2",
 478                 "bpro",
 479                 "bmem",
 480                 "bio",
 481                 "bperi",
 482         };
 483
 484         for (i = 0; i < ARRAY_SIZE(bucks); i++) {
 485                 ret = regulator_get_by_devname(bucks[i], &reg);
 486                 if (reg < 0) {
 487                         printf("%s(): Unable to get regulator %s: %d\n",
 488                                __func__, bucks[i], ret);
 489                         continue;
 490                 }
 491                 regulator_set_mode(reg, DA9063_BUCKMODE_SYNC);
 492         }
 493 }
 494
 495 int board_late_init(void)
 496 {
 497         process_vpd(&vpd);
 498
 499 #ifdef CONFIG_CMD_BMODE
 500         add_board_boot_modes(board_boot_modes);
 501 #endif
 502
 503         if (is_b850v3())
 504                 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
 505         else
 506                 env_set("videoargs", "video=LVDS-1:1024x768@65");
 507
 508         /* board specific pmic init */
 509         pmic_init();
 510
 511         check_time();
 512
 513         pci_init();
 514
 515         return 0;
 516 }
 517
 518 /*
 519  * Removes the 'eth[0-9]*addr' environment variable with the given index
 520  *
 521  * @param index [in] the index of the eth_device whose variable is to be removed
 522  */
 523 static void remove_ethaddr_env_var(int index)
 524 {
 525         char env_var_name[9];
 526
 527         sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
 528         env_set(env_var_name, NULL);
 529 }
 530
 531 int last_stage_init(void)
 532 {
 533         int i;
 534
 535         /*
 536          * Remove first three ethaddr which may have been created by
 537          * function process_vpd().
 538          */
 539         for (i = 0; i < 3; ++i)
 540                 remove_ethaddr_env_var(i);
 541
 542         return 0;
 543 }
 544
 545 int checkboard(void)
 546 {
 547         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 548         return 0;
 549 }
 550
 551 #ifdef CONFIG_OF_BOARD_SETUP
 552 int ft_board_setup(void *blob, bd_t *bd)
 553 {
 554         char *rtc_status = env_get("rtc_status");
 555
 556         fdt_setprop(blob, 0, "ge,boot-ver", version_string,
 557                     strlen(version_string) + 1);
 558
 559         fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
 560                     strlen(rtc_status) + 1);
 561         return 0;
 562 }
 563 #endif
 564
 565 int board_fit_config_name_match(const char *name)
 566 {
 567         if (!vpd.is_read)
 568                 return strcmp(name, "imx6q-bx50v3");
 569
 570         switch (vpd.product_id) {
 571         case VPD_PRODUCT_B450:
 572                 return strcmp(name, "imx6q-b450v3");
 573         case VPD_PRODUCT_B650:
 574                 return strcmp(name, "imx6q-b650v3");
 575         case VPD_PRODUCT_B850:
 576                 return strcmp(name, "imx6q-b850v3");
 577         default:
 578                 return -1;
 579         }
 580 }
 581
 582 int embedded_dtb_select(void)
 583 {
 584         vpd.is_read = false;
 585         return fdtdec_setup();
 586 }