board/ge/bx50v3/bx50v3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Timesys Corporation
   4  * Copyright 2015 General Electric Company
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/mx6-pins.h>
  12 #include <linux/errno.h>
  13 #include <asm/gpio.h>
  14 #include <asm/mach-imx/mxc_i2c.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/mach-imx/video.h>
  18 #include <mmc.h>
  19 #include <fsl_esdhc.h>
  20 #include <miiphy.h>
  21 #include <net.h>
  22 #include <netdev.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <i2c.h>
  28 #include <input.h>
  29 #include <pwm.h>
  30 #include <stdlib.h>
  31 #include "../common/ge_common.h"
  32 #include "../common/vpd_reader.h"
  33 #include "../../../drivers/net/e1000.h"
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 struct vpd_cache;
  37
  38 static int confidx = 3;  /* Default to b850v3. */
  39 static struct vpd_cache vpd;
  40
  41 #ifndef CONFIG_SYS_I2C_EEPROM_ADDR
  42 # define CONFIG_SYS_I2C_EEPROM_ADDR     0x50
  43 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  44 #endif
  45
  46 #ifndef CONFIG_SYS_I2C_EEPROM_BUS
  47 #define CONFIG_SYS_I2C_EEPROM_BUS       4
  48 #endif
  49
  50 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  51         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  52         PAD_CTL_HYS)
  53
  54 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  55         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  56         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  57
  58 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  59         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  60         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  61
  62 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  63         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  64
  65 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  66         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  67
  68 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  69         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  70
  71 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  72                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  73
  74 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  75         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  76         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  77
  78 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  79
  80 int dram_init(void)
  81 {
  82         gd->ram_size = imx_ddr_size();
  83
  84         return 0;
  85 }
  86
  87 static iomux_v3_cfg_t const uart3_pads[] = {
  88         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  89         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  90         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  91         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  92 };
  93
  94 static iomux_v3_cfg_t const uart4_pads[] = {
  95         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  96         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  97 };
  98
  99 static iomux_v3_cfg_t const enet_pads[] = {
 100         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
 101         MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
 102         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 103         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 104         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 105         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 106         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 107         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 108         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 109         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 110         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 111         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 112         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 113         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 114         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 115         /* AR8033 PHY Reset */
 116         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 117 };
 118
 119 static void setup_iomux_enet(void)
 120 {
 121         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 122
 123         /* Reset AR8033 PHY */
 124         gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
 125         mdelay(10);
 126         gpio_set_value(IMX_GPIO_NR(1, 28), 1);
 127         mdelay(1);
 128 }
 129
 130 static iomux_v3_cfg_t const usdhc2_pads[] = {
 131         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(NO_PAD_CTRL),
 138 };
 139
 140 static iomux_v3_cfg_t const usdhc3_pads[] = {
 141         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 147         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 148         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 149         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 150         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 152 };
 153
 154 static iomux_v3_cfg_t const usdhc4_pads[] = {
 155         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 156         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 157         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 158         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 159         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 160         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 161         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 162         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 163         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 164         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 166         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 167 };
 168
 169 static iomux_v3_cfg_t const ecspi1_pads[] = {
 170         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 171         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 172         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 173         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 174 };
 175
 176 static struct i2c_pads_info i2c_pad_info1 = {
 177         .scl = {
 178                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
 179                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
 180                 .gp = IMX_GPIO_NR(5, 27)
 181         },
 182         .sda = {
 183                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
 184                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
 185                 .gp = IMX_GPIO_NR(5, 26)
 186         }
 187 };
 188
 189 static struct i2c_pads_info i2c_pad_info2 = {
 190         .scl = {
 191                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 192                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 193                 .gp = IMX_GPIO_NR(4, 12)
 194         },
 195         .sda = {
 196                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 197                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 198                 .gp = IMX_GPIO_NR(4, 13)
 199         }
 200 };
 201
 202 static struct i2c_pads_info i2c_pad_info3 = {
 203         .scl = {
 204                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
 205                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
 206                 .gp = IMX_GPIO_NR(1, 3)
 207         },
 208         .sda = {
 209                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 210                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 211                 .gp = IMX_GPIO_NR(1, 6)
 212         }
 213 };
 214
 215 #ifdef CONFIG_MXC_SPI
 216 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 217 {
 218         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
 219 }
 220
 221 static void setup_spi(void)
 222 {
 223         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 224 }
 225 #endif
 226
 227 static iomux_v3_cfg_t const pcie_pads[] = {
 228         MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 229         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 230 };
 231
 232 static void setup_pcie(void)
 233 {
 234         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 235 }
 236
 237 static void setup_iomux_uart(void)
 238 {
 239         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 240         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 241 }
 242
 243 #ifdef CONFIG_FSL_ESDHC
 244 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 245         {USDHC2_BASE_ADDR},
 246         {USDHC3_BASE_ADDR},
 247         {USDHC4_BASE_ADDR},
 248 };
 249
 250 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 251 #define USDHC4_CD_GPIO  IMX_GPIO_NR(6, 11)
 252
 253 int board_mmc_getcd(struct mmc *mmc)
 254 {
 255         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 256         int ret = 0;
 257
 258         switch (cfg->esdhc_base) {
 259         case USDHC2_BASE_ADDR:
 260                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 261                 break;
 262         case USDHC3_BASE_ADDR:
 263                 ret = 1; /* eMMC is always present */
 264                 break;
 265         case USDHC4_BASE_ADDR:
 266                 ret = !gpio_get_value(USDHC4_CD_GPIO);
 267                 break;
 268         }
 269
 270         return ret;
 271 }
 272
 273 int board_mmc_init(bd_t *bis)
 274 {
 275         int ret;
 276         int i;
 277
 278         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 279                 switch (i) {
 280                 case 0:
 281                         imx_iomux_v3_setup_multiple_pads(
 282                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 283                         gpio_direction_input(USDHC2_CD_GPIO);
 284                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 285                         break;
 286                 case 1:
 287                         imx_iomux_v3_setup_multiple_pads(
 288                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 289                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 290                         break;
 291                 case 2:
 292                         imx_iomux_v3_setup_multiple_pads(
 293                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 294                         gpio_direction_input(USDHC4_CD_GPIO);
 295                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 296                         break;
 297                 default:
 298                         printf("Warning: you configured more USDHC controllers\n"
 299                                "(%d) then supported by the board (%d)\n",
 300                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 301                         return -EINVAL;
 302                 }
 303
 304                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 305                 if (ret)
 306                         return ret;
 307         }
 308
 309         return 0;
 310 }
 311 #endif
 312
 313 static int mx6_rgmii_rework(struct phy_device *phydev)
 314 {
 315         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
 316         /* set device address 0x7 */
 317         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 318         /* offset 0x8016: CLK_25M Clock Select */
 319         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 320         /* enable register write, no post increment, address 0x7 */
 321         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 322         /* set to 125 MHz from local PLL source */
 323         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 324
 325         /* rgmii tx clock delay enable */
 326         /* set debug port address: SerDes Test and System Mode Control */
 327         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 328         /* enable rgmii tx clock delay */
 329         /* set the reserved bits to avoid board specific voltage peak issue*/
 330         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 331
 332         return 0;
 333 }
 334
 335 int board_phy_config(struct phy_device *phydev)
 336 {
 337         mx6_rgmii_rework(phydev);
 338
 339         if (phydev->drv->config)
 340                 phydev->drv->config(phydev);
 341
 342         return 0;
 343 }
 344
 345 #if defined(CONFIG_VIDEO_IPUV3)
 346 static iomux_v3_cfg_t const backlight_pads[] = {
 347         /* Power for LVDS Display */
 348         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 349 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 350         /* Backlight enable for LVDS display */
 351         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 352 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 353         /* backlight PWM brightness control */
 354         MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 355 };
 356
 357 static void do_enable_hdmi(struct display_info_t const *dev)
 358 {
 359         imx_enable_hdmi_phy();
 360 }
 361
 362 int board_cfb_skip(void)
 363 {
 364         gpio_direction_output(LVDS_POWER_GP, 1);
 365
 366         return 0;
 367 }
 368
 369 static int is_b850v3(void)
 370 {
 371         return confidx == 3;
 372 }
 373
 374 static int detect_lcd(struct display_info_t const *dev)
 375 {
 376         return !is_b850v3();
 377 }
 378
 379 struct display_info_t const displays[] = {{
 380         .bus    = -1,
 381         .addr   = -1,
 382         .pixfmt = IPU_PIX_FMT_RGB24,
 383         .detect = detect_lcd,
 384         .enable = NULL,
 385         .mode   = {
 386                 .name           = "G121X1-L03",
 387                 .refresh        = 60,
 388                 .xres           = 1024,
 389                 .yres           = 768,
 390                 .pixclock       = 15385,
 391                 .left_margin    = 20,
 392                 .right_margin   = 300,
 393                 .upper_margin   = 30,
 394                 .lower_margin   = 8,
 395                 .hsync_len      = 1,
 396                 .vsync_len      = 1,
 397                 .sync           = FB_SYNC_EXT,
 398                 .vmode          = FB_VMODE_NONINTERLACED
 399 } }, {
 400         .bus    = -1,
 401         .addr   = 3,
 402         .pixfmt = IPU_PIX_FMT_RGB24,
 403         .detect = detect_hdmi,
 404         .enable = do_enable_hdmi,
 405         .mode   = {
 406                 .name           = "HDMI",
 407                 .refresh        = 60,
 408                 .xres           = 1024,
 409                 .yres           = 768,
 410                 .pixclock       = 15385,
 411                 .left_margin    = 220,
 412                 .right_margin   = 40,
 413                 .upper_margin   = 21,
 414                 .lower_margin   = 7,
 415                 .hsync_len      = 60,
 416                 .vsync_len      = 10,
 417                 .sync           = FB_SYNC_EXT,
 418                 .vmode          = FB_VMODE_NONINTERLACED
 419 } } };
 420 size_t display_count = ARRAY_SIZE(displays);
 421
 422 static void enable_videopll(void)
 423 {
 424         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 425         s32 timeout = 100000;
 426
 427         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 428
 429         /* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
 430          *   |
 431          * PLL5
 432          *   |
 433          * CS2CDR[LDB_DI0_CLK_SEL]
 434          *   |
 435          *   +----> LDB_DI0_SERIAL_CLK_ROOT
 436          *   |
 437          *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
 438          */
 439
 440         clrsetbits_le32(&ccm->analog_pll_video,
 441                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 442                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 443                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 444                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 445
 446         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 447         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 448
 449         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 450
 451         while (timeout--)
 452                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 453                         break;
 454
 455         if (timeout < 0)
 456                 printf("Warning: video pll lock timeout!\n");
 457
 458         clrsetbits_le32(&ccm->analog_pll_video,
 459                         BM_ANADIG_PLL_VIDEO_BYPASS,
 460                         BM_ANADIG_PLL_VIDEO_ENABLE);
 461 }
 462
 463 static void setup_display_b850v3(void)
 464 {
 465         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 466         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 467
 468         enable_videopll();
 469
 470         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 471         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 472
 473         imx_setup_hdmi();
 474
 475         /* Set LDB_DI0 as clock source for IPU_DI0 */
 476         clrsetbits_le32(&mxc_ccm->chsccdr,
 477                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 478                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 479                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 480
 481         /* Turn on IPU LDB DI0 clocks */
 482         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 483
 484         enable_ipu_clock();
 485
 486         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 487                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 488                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 489                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 490                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 491                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 492                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 493                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 494                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 495                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 496                &iomux->gpr[2]);
 497
 498         clrbits_le32(&iomux->gpr[3],
 499                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 500                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 501                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 502 }
 503
 504 static void setup_display_bx50v3(void)
 505 {
 506         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 507         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 508
 509         enable_videopll();
 510
 511         /* When a reset/reboot is performed the display power needs to be turned
 512          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 513          * an additional 200ms here. Unfortunately we use external PMIC for
 514          * doing the reset, so can not differentiate between POR vs soft reset
 515          */
 516         mdelay(200);
 517
 518         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 519         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 520
 521         /* Set LDB_DI0 as clock source for IPU_DI0 */
 522         clrsetbits_le32(&mxc_ccm->chsccdr,
 523                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 524                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 525                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 526
 527         /* Turn on IPU LDB DI0 clocks */
 528         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 529
 530         enable_ipu_clock();
 531
 532         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 533                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 534                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 535                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 536                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 537                &iomux->gpr[2]);
 538
 539         clrsetbits_le32(&iomux->gpr[3],
 540                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 541                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 542                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 543
 544         /* backlights off until needed */
 545         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 546                                          ARRAY_SIZE(backlight_pads));
 547         gpio_direction_input(LVDS_POWER_GP);
 548         gpio_direction_input(LVDS_BACKLIGHT_GP);
 549 }
 550 #endif /* CONFIG_VIDEO_IPUV3 */
 551
 552 /*
 553  * Do not overwrite the console
 554  * Use always serial for U-Boot console
 555  */
 556 int overwrite_console(void)
 557 {
 558         return 1;
 559 }
 560
 561 #define VPD_TYPE_INVALID 0x00
 562 #define VPD_BLOCK_NETWORK 0x20
 563 #define VPD_BLOCK_HWID 0x44
 564 #define VPD_PRODUCT_B850 1
 565 #define VPD_PRODUCT_B650 2
 566 #define VPD_PRODUCT_B450 3
 567 #define VPD_HAS_MAC1 0x1
 568 #define VPD_HAS_MAC2 0x2
 569 #define VPD_MAC_ADDRESS_LENGTH 6
 570
 571 struct vpd_cache {
 572         u8 product_id;
 573         u8 has;
 574         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 575         unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
 576 };
 577
 578 /*
 579  * Extracts MAC and product information from the VPD.
 580  */
 581 static int vpd_callback(void *userdata, u8 id, u8 version, u8 type,
 582                         size_t size, u8 const *data)
 583 {
 584         struct vpd_cache *vpd = (struct vpd_cache *)userdata;
 585
 586         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 587             size >= 1) {
 588                 vpd->product_id = data[0];
 589         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 590                    type != VPD_TYPE_INVALID) {
 591                 if (size >= 6) {
 592                         vpd->has |= VPD_HAS_MAC1;
 593                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 594                 }
 595                 if (size >= 12) {
 596                         vpd->has |= VPD_HAS_MAC2;
 597                         memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
 598                 }
 599         }
 600
 601         return 0;
 602 }
 603
 604 static void process_vpd(struct vpd_cache *vpd)
 605 {
 606         int fec_index = -1;
 607         int i210_index = -1;
 608
 609         switch (vpd->product_id) {
 610         case VPD_PRODUCT_B450:
 611                 env_set("confidx", "1");
 612                 i210_index = 0;
 613                 fec_index = 1;
 614                 break;
 615         case VPD_PRODUCT_B650:
 616                 env_set("confidx", "2");
 617                 i210_index = 0;
 618                 fec_index = 1;
 619                 break;
 620         case VPD_PRODUCT_B850:
 621                 env_set("confidx", "3");
 622                 i210_index = 1;
 623                 fec_index = 2;
 624                 break;
 625         }
 626
 627         if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
 628                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 629
 630         if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 631                 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 632 }
 633
 634 static int read_vpd(uint eeprom_bus)
 635 {
 636         int res;
 637         int size = 1024;
 638         uint8_t *data;
 639         unsigned int current_i2c_bus = i2c_get_bus_num();
 640
 641         res = i2c_set_bus_num(eeprom_bus);
 642         if (res < 0)
 643                 return res;
 644
 645         data = (uint8_t *)malloc(size);
 646         if (!data)
 647                 return -ENOMEM;
 648
 649         res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
 650                         CONFIG_SYS_I2C_EEPROM_ADDR_LEN, data, size);
 651
 652         if (res == 0) {
 653                 memset(&vpd, 0, sizeof(vpd));
 654                 vpd_reader(size, data, &vpd, vpd_callback);
 655         }
 656
 657         free(data);
 658
 659         i2c_set_bus_num(current_i2c_bus);
 660         return res;
 661 }
 662
 663 int board_eth_init(bd_t *bis)
 664 {
 665         setup_iomux_enet();
 666         setup_pcie();
 667
 668         e1000_initialize(bis);
 669
 670         return cpu_eth_init(bis);
 671 }
 672
 673 static iomux_v3_cfg_t const misc_pads[] = {
 674         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 675         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 676         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 677         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 678         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 679         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 680         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 681         MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 682 };
 683 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 684 #define WIFI_EN IMX_GPIO_NR(6, 14)
 685
 686 int board_early_init_f(void)
 687 {
 688         imx_iomux_v3_setup_multiple_pads(misc_pads,
 689                                          ARRAY_SIZE(misc_pads));
 690
 691         setup_iomux_uart();
 692
 693 #if defined(CONFIG_VIDEO_IPUV3)
 694         /* Set LDB clock to Video PLL */
 695         select_ldb_di_clock_source(MXC_PLL5_CLK);
 696 #endif
 697         return 0;
 698 }
 699
 700 static void set_confidx(const struct vpd_cache* vpd)
 701 {
 702         switch (vpd->product_id) {
 703         case VPD_PRODUCT_B450:
 704                 confidx = 1;
 705                 break;
 706         case VPD_PRODUCT_B650:
 707                 confidx = 2;
 708                 break;
 709         case VPD_PRODUCT_B850:
 710                 confidx = 3;
 711                 break;
 712         }
 713 }
 714
 715 int board_init(void)
 716 {
 717         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 718         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 719         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 720
 721         read_vpd(CONFIG_SYS_I2C_EEPROM_BUS);
 722
 723         set_confidx(&vpd);
 724
 725         gpio_direction_output(SUS_S3_OUT, 1);
 726         gpio_direction_output(WIFI_EN, 1);
 727 #if defined(CONFIG_VIDEO_IPUV3)
 728         if (is_b850v3())
 729                 setup_display_b850v3();
 730         else
 731                 setup_display_bx50v3();
 732 #endif
 733         /* address of boot parameters */
 734         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 735
 736 #ifdef CONFIG_MXC_SPI
 737         setup_spi();
 738 #endif
 739         return 0;
 740 }
 741
 742 #ifdef CONFIG_CMD_BMODE
 743 static const struct boot_mode board_boot_modes[] = {
 744         /* 4 bit bus width */
 745         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 746         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 747         {NULL,   0},
 748 };
 749 #endif
 750
 751 void pmic_init(void)
 752 {
 753 #define I2C_PMIC                0x2
 754 #define DA9063_I2C_ADDR         0x58
 755 #define DA9063_REG_BCORE2_CFG   0x9D
 756 #define DA9063_REG_BCORE1_CFG   0x9E
 757 #define DA9063_REG_BPRO_CFG     0x9F
 758 #define DA9063_REG_BIO_CFG      0xA0
 759 #define DA9063_REG_BMEM_CFG     0xA1
 760 #define DA9063_REG_BPERI_CFG    0xA2
 761 #define DA9063_BUCK_MODE_MASK   0xC0
 762 #define DA9063_BUCK_MODE_MANUAL 0x00
 763 #define DA9063_BUCK_MODE_SLEEP  0x40
 764 #define DA9063_BUCK_MODE_SYNC   0x80
 765 #define DA9063_BUCK_MODE_AUTO   0xC0
 766
 767         uchar val;
 768
 769         i2c_set_bus_num(I2C_PMIC);
 770
 771         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 772         val &= ~DA9063_BUCK_MODE_MASK;
 773         val |= DA9063_BUCK_MODE_SYNC;
 774         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 775
 776         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 777         val &= ~DA9063_BUCK_MODE_MASK;
 778         val |= DA9063_BUCK_MODE_SYNC;
 779         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 780
 781         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 782         val &= ~DA9063_BUCK_MODE_MASK;
 783         val |= DA9063_BUCK_MODE_SYNC;
 784         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 785
 786         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 787         val &= ~DA9063_BUCK_MODE_MASK;
 788         val |= DA9063_BUCK_MODE_SYNC;
 789         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 790
 791         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 792         val &= ~DA9063_BUCK_MODE_MASK;
 793         val |= DA9063_BUCK_MODE_SYNC;
 794         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 795
 796         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 797         val &= ~DA9063_BUCK_MODE_MASK;
 798         val |= DA9063_BUCK_MODE_SYNC;
 799         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 800 }
 801
 802 int board_late_init(void)
 803 {
 804         process_vpd(&vpd);
 805
 806 #ifdef CONFIG_CMD_BMODE
 807         add_board_boot_modes(board_boot_modes);
 808 #endif
 809
 810         if (is_b850v3())
 811                 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
 812         else
 813                 env_set("videoargs", "video=LVDS-1:1024x768@65");
 814
 815         /* board specific pmic init */
 816         pmic_init();
 817
 818         check_time();
 819
 820         return 0;
 821 }
 822
 823 /*
 824  * Removes the 'eth[0-9]*addr' environment variable with the given index
 825  *
 826  * @param index [in] the index of the eth_device whose variable is to be removed
 827  */
 828 static void remove_ethaddr_env_var(int index)
 829 {
 830         char env_var_name[9];
 831
 832         sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
 833         env_set(env_var_name, NULL);
 834 }
 835
 836 int last_stage_init(void)
 837 {
 838         int i;
 839
 840         /*
 841          * Remove first three ethaddr which may have been created by
 842          * function process_vpd().
 843          */
 844         for (i = 0; i < 3; ++i)
 845                 remove_ethaddr_env_var(i);
 846
 847         return 0;
 848 }
 849
 850 int checkboard(void)
 851 {
 852         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 853         return 0;
 854 }
 855
 856 static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 857 {
 858 #ifdef CONFIG_VIDEO_IPUV3
 859         /* We need at least 200ms between power on and backlight on
 860          * as per specifications from CHI MEI */
 861         mdelay(250);
 862
 863         /* enable backlight PWM 1 */
 864         pwm_init(0, 0, 0);
 865
 866         /* duty cycle 5000000ns, period: 5000000ns */
 867         pwm_config(0, 5000000, 5000000);
 868
 869         /* Backlight Power */
 870         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 871
 872         pwm_enable(0);
 873 #endif
 874
 875         return 0;
 876 }
 877
 878 U_BOOT_CMD(
 879        bx50_backlight_enable, 1,      1,      do_backlight_enable,
 880        "enable Bx50 backlight",
 881        ""
 882 );