board/ge/bx50v3/bx50v3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Timesys Corporation
   4  * Copyright 2015 General Electric Company
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <init.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <env.h>
  14 #include <linux/errno.h>
  15 #include <linux/libfdt.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/boot_mode.h>
  19 #include <asm/mach-imx/video.h>
  20 #include <mmc.h>
  21 #include <fsl_esdhc_imx.h>
  22 #include <miiphy.h>
  23 #include <net.h>
  24 #include <netdev.h>
  25 #include <asm/arch/mxc_hdmi.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/io.h>
  28 #include <asm/arch/sys_proto.h>
  29 #include <power/regulator.h>
  30 #include <power/da9063_pmic.h>
  31 #include <input.h>
  32 #include <pwm.h>
  33 #include <version.h>
  34 #include <stdlib.h>
  35 #include <dm/root.h>
  36 #include "../common/ge_common.h"
  37 #include "../common/vpd_reader.h"
  38 #include "../../../drivers/net/e1000.h"
  39 #include <pci.h>
  40 #include <panel.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 static int confidx;  /* Default to generic. */
  45 static struct vpd_cache vpd;
  46
  47 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  48         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  49         PAD_CTL_HYS)
  50
  51 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  52         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  53         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  54
  55 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  56         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  57
  58 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  59         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  60
  61 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  62         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  63
  64 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  65         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  66         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  67
  68 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  69
  70 int dram_init(void)
  71 {
  72         gd->ram_size = imx_ddr_size();
  73
  74         return 0;
  75 }
  76
  77 static iomux_v3_cfg_t const uart3_pads[] = {
  78         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  79         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  80         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  81         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  82 };
  83
  84 static iomux_v3_cfg_t const uart4_pads[] = {
  85         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  86         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  87 };
  88
  89 static void setup_iomux_uart(void)
  90 {
  91         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
  92         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  93 }
  94
  95 static int mx6_rgmii_rework(struct phy_device *phydev)
  96 {
  97         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
  98         /* set device address 0x7 */
  99         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 100         /* offset 0x8016: CLK_25M Clock Select */
 101         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 102         /* enable register write, no post increment, address 0x7 */
 103         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 104         /* set to 125 MHz from local PLL source */
 105         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 106
 107         /* rgmii tx clock delay enable */
 108         /* set debug port address: SerDes Test and System Mode Control */
 109         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 110         /* enable rgmii tx clock delay */
 111         /* set the reserved bits to avoid board specific voltage peak issue*/
 112         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 113
 114         return 0;
 115 }
 116
 117 int board_phy_config(struct phy_device *phydev)
 118 {
 119         mx6_rgmii_rework(phydev);
 120
 121         if (phydev->drv->config)
 122                 phydev->drv->config(phydev);
 123
 124         return 0;
 125 }
 126
 127 #if defined(CONFIG_VIDEO_IPUV3)
 128 static void do_enable_backlight(struct display_info_t const *dev)
 129 {
 130         struct udevice *panel;
 131         int ret;
 132
 133         ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
 134         if (ret) {
 135                 printf("Could not find panel: %d\n", ret);
 136                 return;
 137         }
 138
 139         panel_set_backlight(panel, 100);
 140         panel_enable_backlight(panel);
 141 }
 142
 143 static void do_enable_hdmi(struct display_info_t const *dev)
 144 {
 145         imx_enable_hdmi_phy();
 146 }
 147
 148 static int is_b850v3(void)
 149 {
 150         return confidx == 3;
 151 }
 152
 153 static int detect_lcd(struct display_info_t const *dev)
 154 {
 155         return !is_b850v3();
 156 }
 157
 158 struct display_info_t const displays[] = {{
 159         .bus    = -1,
 160         .addr   = -1,
 161         .pixfmt = IPU_PIX_FMT_RGB24,
 162         .detect = detect_lcd,
 163         .enable = do_enable_backlight,
 164         .mode   = {
 165                 .name           = "G121X1-L03",
 166                 .refresh        = 60,
 167                 .xres           = 1024,
 168                 .yres           = 768,
 169                 .pixclock       = 15385,
 170                 .left_margin    = 20,
 171                 .right_margin   = 300,
 172                 .upper_margin   = 30,
 173                 .lower_margin   = 8,
 174                 .hsync_len      = 1,
 175                 .vsync_len      = 1,
 176                 .sync           = FB_SYNC_EXT,
 177                 .vmode          = FB_VMODE_NONINTERLACED
 178 } }, {
 179         .bus    = -1,
 180         .addr   = 3,
 181         .pixfmt = IPU_PIX_FMT_RGB24,
 182         .detect = detect_hdmi,
 183         .enable = do_enable_hdmi,
 184         .mode   = {
 185                 .name           = "HDMI",
 186                 .refresh        = 60,
 187                 .xres           = 1024,
 188                 .yres           = 768,
 189                 .pixclock       = 15385,
 190                 .left_margin    = 220,
 191                 .right_margin   = 40,
 192                 .upper_margin   = 21,
 193                 .lower_margin   = 7,
 194                 .hsync_len      = 60,
 195                 .vsync_len      = 10,
 196                 .sync           = FB_SYNC_EXT,
 197                 .vmode          = FB_VMODE_NONINTERLACED
 198 } } };
 199 size_t display_count = ARRAY_SIZE(displays);
 200
 201 static void enable_videopll(void)
 202 {
 203         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 204         s32 timeout = 100000;
 205
 206         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 207
 208         /* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
 209          *   |
 210          * PLL5
 211          *   |
 212          * CS2CDR[LDB_DI0_CLK_SEL]
 213          *   |
 214          *   +----> LDB_DI0_SERIAL_CLK_ROOT
 215          *   |
 216          *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
 217          */
 218
 219         clrsetbits_le32(&ccm->analog_pll_video,
 220                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 221                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 222                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 223                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 224
 225         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 226         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 227
 228         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 229
 230         while (timeout--)
 231                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 232                         break;
 233
 234         if (timeout < 0)
 235                 printf("Warning: video pll lock timeout!\n");
 236
 237         clrsetbits_le32(&ccm->analog_pll_video,
 238                         BM_ANADIG_PLL_VIDEO_BYPASS,
 239                         BM_ANADIG_PLL_VIDEO_ENABLE);
 240 }
 241
 242 static void setup_display_b850v3(void)
 243 {
 244         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 245         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 246
 247         enable_videopll();
 248
 249         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 250         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 251
 252         imx_setup_hdmi();
 253
 254         /* Set LDB_DI0 as clock source for IPU_DI0 */
 255         clrsetbits_le32(&mxc_ccm->chsccdr,
 256                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 257                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 258                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 259
 260         /* Turn on IPU LDB DI0 clocks */
 261         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 262
 263         enable_ipu_clock();
 264
 265         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 266                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 267                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 268                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 269                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 270                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 271                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 272                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 273                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 274                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 275                &iomux->gpr[2]);
 276
 277         clrbits_le32(&iomux->gpr[3],
 278                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 279                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 280                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 281 }
 282
 283 static void setup_display_bx50v3(void)
 284 {
 285         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 286         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 287
 288         enable_videopll();
 289
 290         /* When a reset/reboot is performed the display power needs to be turned
 291          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 292          * an additional 200ms here. Unfortunately we use external PMIC for
 293          * doing the reset, so can not differentiate between POR vs soft reset
 294          */
 295         mdelay(200);
 296
 297         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 298         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 299
 300         /* Set LDB_DI0 as clock source for IPU_DI0 */
 301         clrsetbits_le32(&mxc_ccm->chsccdr,
 302                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 303                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 304                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 305
 306         /* Turn on IPU LDB DI0 clocks */
 307         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 308
 309         enable_ipu_clock();
 310
 311         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 312                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 313                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 314                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 315                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 316                &iomux->gpr[2]);
 317
 318         clrsetbits_le32(&iomux->gpr[3],
 319                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 320                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 321                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 322 }
 323 #endif /* CONFIG_VIDEO_IPUV3 */
 324
 325 /*
 326  * Do not overwrite the console
 327  * Use always serial for U-Boot console
 328  */
 329 int overwrite_console(void)
 330 {
 331         return 1;
 332 }
 333
 334 #define VPD_TYPE_INVALID 0x00
 335 #define VPD_BLOCK_NETWORK 0x20
 336 #define VPD_BLOCK_HWID 0x44
 337 #define VPD_PRODUCT_B850 1
 338 #define VPD_PRODUCT_B650 2
 339 #define VPD_PRODUCT_B450 3
 340 #define VPD_HAS_MAC1 0x1
 341 #define VPD_HAS_MAC2 0x2
 342 #define VPD_MAC_ADDRESS_LENGTH 6
 343
 344 struct vpd_cache {
 345         bool is_read;
 346         u8 product_id;
 347         u8 has;
 348         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 349         unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
 350 };
 351
 352 /*
 353  * Extracts MAC and product information from the VPD.
 354  */
 355 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
 356                         size_t size, u8 const *data)
 357 {
 358         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 359             size >= 1) {
 360                 vpd->product_id = data[0];
 361         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 362                    type != VPD_TYPE_INVALID) {
 363                 if (size >= 6) {
 364                         vpd->has |= VPD_HAS_MAC1;
 365                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 366                 }
 367                 if (size >= 12) {
 368                         vpd->has |= VPD_HAS_MAC2;
 369                         memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
 370                 }
 371         }
 372
 373         return 0;
 374 }
 375
 376 static void process_vpd(struct vpd_cache *vpd)
 377 {
 378         int fec_index = 0;
 379         int i210_index = -1;
 380
 381         if (!vpd->is_read) {
 382                 printf("VPD wasn't read");
 383                 return;
 384         }
 385
 386         if (vpd->has & VPD_HAS_MAC1)
 387                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 388
 389         env_set("ethact", "eth0");
 390
 391         switch (vpd->product_id) {
 392         case VPD_PRODUCT_B450:
 393                 env_set("confidx", "1");
 394                 i210_index = 1;
 395                 break;
 396         case VPD_PRODUCT_B650:
 397                 env_set("confidx", "2");
 398                 i210_index = 1;
 399                 break;
 400         case VPD_PRODUCT_B850:
 401                 env_set("confidx", "3");
 402                 i210_index = 2;
 403                 break;
 404         }
 405
 406         if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 407                 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 408 }
 409
 410 static iomux_v3_cfg_t const misc_pads[] = {
 411         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 412         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 413         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 414         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 415         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 416         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 417         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 418         MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 419 };
 420 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 421 #define WIFI_EN IMX_GPIO_NR(6, 14)
 422
 423 int board_early_init_f(void)
 424 {
 425         imx_iomux_v3_setup_multiple_pads(misc_pads,
 426                                          ARRAY_SIZE(misc_pads));
 427
 428         setup_iomux_uart();
 429
 430 #if defined(CONFIG_VIDEO_IPUV3)
 431         /* Set LDB clock to Video PLL */
 432         select_ldb_di_clock_source(MXC_PLL5_CLK);
 433 #endif
 434         return 0;
 435 }
 436
 437 static void set_confidx(const struct vpd_cache* vpd)
 438 {
 439         switch (vpd->product_id) {
 440         case VPD_PRODUCT_B450:
 441                 confidx = 1;
 442                 break;
 443         case VPD_PRODUCT_B650:
 444                 confidx = 2;
 445                 break;
 446         case VPD_PRODUCT_B850:
 447                 confidx = 3;
 448                 break;
 449         }
 450 }
 451
 452 int board_init(void)
 453 {
 454         if (!read_vpd(&vpd, vpd_callback)) {
 455                 int ret, rescan;
 456
 457                 vpd.is_read = true;
 458                 set_confidx(&vpd);
 459
 460                 ret = fdtdec_resetup(&rescan);
 461                 if (!ret && rescan) {
 462                         dm_uninit();
 463                         dm_init_and_scan(false);
 464                 }
 465         }
 466
 467         gpio_request(SUS_S3_OUT, "sus_s3_out");
 468         gpio_direction_output(SUS_S3_OUT, 1);
 469
 470         gpio_request(WIFI_EN, "wifi_en");
 471         gpio_direction_output(WIFI_EN, 1);
 472
 473 #if defined(CONFIG_VIDEO_IPUV3)
 474         if (is_b850v3())
 475                 setup_display_b850v3();
 476         else
 477                 setup_display_bx50v3();
 478 #endif
 479
 480         /* address of boot parameters */
 481         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 482
 483         return 0;
 484 }
 485
 486 #ifdef CONFIG_CMD_BMODE
 487 static const struct boot_mode board_boot_modes[] = {
 488         /* 4 bit bus width */
 489         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 490         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 491         {NULL,   0},
 492 };
 493 #endif
 494
 495 void pmic_init(void)
 496 {
 497         struct udevice *reg;
 498         int ret, i;
 499         static const char * const bucks[] = {
 500                 "bcore1",
 501                 "bcore2",
 502                 "bpro",
 503                 "bmem",
 504                 "bio",
 505                 "bperi",
 506         };
 507
 508         for (i = 0; i < ARRAY_SIZE(bucks); i++) {
 509                 ret = regulator_get_by_devname(bucks[i], &reg);
 510                 if (reg < 0) {
 511                         printf("%s(): Unable to get regulator %s: %d\n",
 512                                __func__, bucks[i], ret);
 513                         continue;
 514                 }
 515                 regulator_set_mode(reg, DA9063_BUCKMODE_SYNC);
 516         }
 517 }
 518
 519 int board_late_init(void)
 520 {
 521         process_vpd(&vpd);
 522
 523 #ifdef CONFIG_CMD_BMODE
 524         add_board_boot_modes(board_boot_modes);
 525 #endif
 526
 527         if (is_b850v3())
 528                 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
 529         else
 530                 env_set("videoargs", "video=LVDS-1:1024x768@65");
 531
 532         /* board specific pmic init */
 533         pmic_init();
 534
 535         check_time();
 536
 537         pci_init();
 538
 539         return 0;
 540 }
 541
 542 /*
 543  * Removes the 'eth[0-9]*addr' environment variable with the given index
 544  *
 545  * @param index [in] the index of the eth_device whose variable is to be removed
 546  */
 547 static void remove_ethaddr_env_var(int index)
 548 {
 549         char env_var_name[9];
 550
 551         sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
 552         env_set(env_var_name, NULL);
 553 }
 554
 555 int last_stage_init(void)
 556 {
 557         int i;
 558
 559         /*
 560          * Remove first three ethaddr which may have been created by
 561          * function process_vpd().
 562          */
 563         for (i = 0; i < 3; ++i)
 564                 remove_ethaddr_env_var(i);
 565
 566         return 0;
 567 }
 568
 569 int checkboard(void)
 570 {
 571         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 572         return 0;
 573 }
 574
 575 #ifdef CONFIG_OF_BOARD_SETUP
 576 int ft_board_setup(void *blob, bd_t *bd)
 577 {
 578         char *rtc_status = env_get("rtc_status");
 579
 580         fdt_setprop(blob, 0, "ge,boot-ver", version_string,
 581                     strlen(version_string) + 1);
 582
 583         fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
 584                     strlen(rtc_status) + 1);
 585         return 0;
 586 }
 587 #endif
 588
 589 int board_fit_config_name_match(const char *name)
 590 {
 591         if (!vpd.is_read)
 592                 return strcmp(name, "imx6q-bx50v3");
 593
 594         switch (vpd.product_id) {
 595         case VPD_PRODUCT_B450:
 596                 return strcmp(name, "imx6q-b450v3");
 597         case VPD_PRODUCT_B650:
 598                 return strcmp(name, "imx6q-b650v3");
 599         case VPD_PRODUCT_B850:
 600                 return strcmp(name, "imx6q-b850v3");
 601         default:
 602                 return -1;
 603         }
 604 }
 605
 606 int embedded_dtb_select(void)
 607 {
 608         vpd.is_read = false;
 609         return fdtdec_setup();
 610 }