board/ge/bx50v3/bx50v3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Timesys Corporation
   4  * Copyright 2015 General Electric Company
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <image.h>
   9 #include <init.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <env.h>
  15 #include <linux/delay.h>
  16 #include <linux/errno.h>
  17 #include <linux/libfdt.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/iomux-v3.h>
  20 #include <asm/mach-imx/boot_mode.h>
  21 #include <asm/mach-imx/video.h>
  22 #include <mmc.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <miiphy.h>
  25 #include <net.h>
  26 #include <netdev.h>
  27 #include <asm/arch/mxc_hdmi.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/io.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include <power/regulator.h>
  32 #include <power/da9063_pmic.h>
  33 #include <input.h>
  34 #include <pwm.h>
  35 #include <version.h>
  36 #include <stdlib.h>
  37 #include <dm/root.h>
  38 #include "../common/ge_rtc.h"
  39 #include "../common/vpd_reader.h"
  40 #include "../../../drivers/net/e1000.h"
  41 #include <pci.h>
  42 #include <panel.h>
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 static int confidx;  /* Default to generic. */
  47 static struct vpd_cache vpd;
  48
  49 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  51         PAD_CTL_HYS)
  52
  53 int dram_init(void)
  54 {
  55         gd->ram_size = imx_ddr_size();
  56
  57         return 0;
  58 }
  59
  60 static int mx6_rgmii_rework(struct phy_device *phydev)
  61 {
  62         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
  63         /* set device address 0x7 */
  64         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  65         /* offset 0x8016: CLK_25M Clock Select */
  66         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  67         /* enable register write, no post increment, address 0x7 */
  68         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  69         /* set to 125 MHz from local PLL source */
  70         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
  71
  72         /* rgmii tx clock delay enable */
  73         /* set debug port address: SerDes Test and System Mode Control */
  74         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  75         /* enable rgmii tx clock delay */
  76         /* set the reserved bits to avoid board specific voltage peak issue*/
  77         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
  78
  79         return 0;
  80 }
  81
  82 int board_phy_config(struct phy_device *phydev)
  83 {
  84         mx6_rgmii_rework(phydev);
  85
  86         if (phydev->drv->config)
  87                 phydev->drv->config(phydev);
  88
  89         return 0;
  90 }
  91
  92 #if defined(CONFIG_VIDEO_IPUV3)
  93 static void do_enable_backlight(struct display_info_t const *dev)
  94 {
  95         struct udevice *panel;
  96         int ret;
  97
  98         ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
  99         if (ret) {
 100                 printf("Could not find panel: %d\n", ret);
 101                 return;
 102         }
 103
 104         panel_set_backlight(panel, 100);
 105         panel_enable_backlight(panel);
 106 }
 107
 108 static void do_enable_hdmi(struct display_info_t const *dev)
 109 {
 110         imx_enable_hdmi_phy();
 111 }
 112
 113 static int is_b850v3(void)
 114 {
 115         return confidx == 3;
 116 }
 117
 118 static int detect_lcd(struct display_info_t const *dev)
 119 {
 120         return !is_b850v3();
 121 }
 122
 123 struct display_info_t const displays[] = {{
 124         .bus    = -1,
 125         .addr   = -1,
 126         .pixfmt = IPU_PIX_FMT_RGB24,
 127         .detect = detect_lcd,
 128         .enable = do_enable_backlight,
 129         .mode   = {
 130                 .name           = "G121X1-L03",
 131                 .refresh        = 60,
 132                 .xres           = 1024,
 133                 .yres           = 768,
 134                 .pixclock       = 15385,
 135                 .left_margin    = 20,
 136                 .right_margin   = 300,
 137                 .upper_margin   = 30,
 138                 .lower_margin   = 8,
 139                 .hsync_len      = 1,
 140                 .vsync_len      = 1,
 141                 .sync           = FB_SYNC_EXT,
 142                 .vmode          = FB_VMODE_NONINTERLACED
 143 } }, {
 144         .bus    = -1,
 145         .addr   = 3,
 146         .pixfmt = IPU_PIX_FMT_RGB24,
 147         .detect = detect_hdmi,
 148         .enable = do_enable_hdmi,
 149         .mode   = {
 150                 .name           = "HDMI",
 151                 .refresh        = 60,
 152                 .xres           = 1024,
 153                 .yres           = 768,
 154                 .pixclock       = 15385,
 155                 .left_margin    = 220,
 156                 .right_margin   = 40,
 157                 .upper_margin   = 21,
 158                 .lower_margin   = 7,
 159                 .hsync_len      = 60,
 160                 .vsync_len      = 10,
 161                 .sync           = FB_SYNC_EXT,
 162                 .vmode          = FB_VMODE_NONINTERLACED
 163 } } };
 164 size_t display_count = ARRAY_SIZE(displays);
 165
 166 static void enable_videopll(void)
 167 {
 168         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 169         s32 timeout = 100000;
 170
 171         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 172
 173         /* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
 174          *   |
 175          * PLL5
 176          *   |
 177          * CS2CDR[LDB_DI0_CLK_SEL]
 178          *   |
 179          *   +----> LDB_DI0_SERIAL_CLK_ROOT
 180          *   |
 181          *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
 182          */
 183
 184         clrsetbits_le32(&ccm->analog_pll_video,
 185                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 186                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 187                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 188                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 189
 190         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 191         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 192
 193         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 194
 195         while (timeout--)
 196                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 197                         break;
 198
 199         if (timeout < 0)
 200                 printf("Warning: video pll lock timeout!\n");
 201
 202         clrsetbits_le32(&ccm->analog_pll_video,
 203                         BM_ANADIG_PLL_VIDEO_BYPASS,
 204                         BM_ANADIG_PLL_VIDEO_ENABLE);
 205 }
 206
 207 static void setup_display_b850v3(void)
 208 {
 209         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 210         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 211
 212         enable_videopll();
 213
 214         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 215         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 216
 217         imx_setup_hdmi();
 218
 219         /* Set LDB_DI0 as clock source for IPU_DI0 */
 220         clrsetbits_le32(&mxc_ccm->chsccdr,
 221                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 222                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 223                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 224
 225         /* Turn on IPU LDB DI0 clocks */
 226         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 227
 228         enable_ipu_clock();
 229
 230         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 231                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 232                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 233                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 234                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 235                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 236                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 237                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 238                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 239                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 240                &iomux->gpr[2]);
 241
 242         clrbits_le32(&iomux->gpr[3],
 243                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 244                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 245                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 246 }
 247
 248 static void setup_display_bx50v3(void)
 249 {
 250         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 251         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 252
 253         enable_videopll();
 254
 255         /* When a reset/reboot is performed the display power needs to be turned
 256          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 257          * an additional 200ms here. Unfortunately we use external PMIC for
 258          * doing the reset, so can not differentiate between POR vs soft reset
 259          */
 260         mdelay(200);
 261
 262         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 263         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 264
 265         /* Set LDB_DI0 as clock source for IPU_DI0 */
 266         clrsetbits_le32(&mxc_ccm->chsccdr,
 267                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 268                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 269                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 270
 271         /* Turn on IPU LDB DI0 clocks */
 272         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 273
 274         enable_ipu_clock();
 275
 276         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 277                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 278                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 279                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 280                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 281                &iomux->gpr[2]);
 282
 283         clrsetbits_le32(&iomux->gpr[3],
 284                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 285                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 286                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 287 }
 288 #endif /* CONFIG_VIDEO_IPUV3 */
 289
 290 /*
 291  * Do not overwrite the console
 292  * Use always serial for U-Boot console
 293  */
 294 int overwrite_console(void)
 295 {
 296         return 1;
 297 }
 298
 299 #define VPD_TYPE_INVALID 0x00
 300 #define VPD_BLOCK_NETWORK 0x20
 301 #define VPD_BLOCK_HWID 0x44
 302 #define VPD_PRODUCT_B850 1
 303 #define VPD_PRODUCT_B650 2
 304 #define VPD_PRODUCT_B450 3
 305 #define VPD_HAS_MAC1 0x1
 306 #define VPD_HAS_MAC2 0x2
 307 #define VPD_MAC_ADDRESS_LENGTH 6
 308
 309 struct vpd_cache {
 310         bool is_read;
 311         u8 product_id;
 312         u8 has;
 313         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 314         unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
 315 };
 316
 317 /*
 318  * Extracts MAC and product information from the VPD.
 319  */
 320 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
 321                         size_t size, u8 const *data)
 322 {
 323         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 324             size >= 1) {
 325                 vpd->product_id = data[0];
 326         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 327                    type != VPD_TYPE_INVALID) {
 328                 if (size >= 6) {
 329                         vpd->has |= VPD_HAS_MAC1;
 330                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 331                 }
 332                 if (size >= 12) {
 333                         vpd->has |= VPD_HAS_MAC2;
 334                         memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
 335                 }
 336         }
 337
 338         return 0;
 339 }
 340
 341 static void process_vpd(struct vpd_cache *vpd)
 342 {
 343         int fec_index = 0;
 344         int i210_index = -1;
 345
 346         if (!vpd->is_read) {
 347                 printf("VPD wasn't read");
 348                 return;
 349         }
 350
 351         if (vpd->has & VPD_HAS_MAC1)
 352                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 353
 354         env_set("ethact", "eth0");
 355
 356         switch (vpd->product_id) {
 357         case VPD_PRODUCT_B450:
 358                 env_set("confidx", "1");
 359                 i210_index = 1;
 360                 break;
 361         case VPD_PRODUCT_B650:
 362                 env_set("confidx", "2");
 363                 i210_index = 1;
 364                 break;
 365         case VPD_PRODUCT_B850:
 366                 env_set("confidx", "3");
 367                 i210_index = 2;
 368                 break;
 369         }
 370
 371         if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 372                 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 373 }
 374
 375 static iomux_v3_cfg_t const misc_pads[] = {
 376         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 377         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 378         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 379         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 380         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 381         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 382         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 383         MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 384 };
 385 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 386 #define WIFI_EN IMX_GPIO_NR(6, 14)
 387
 388 int board_early_init_f(void)
 389 {
 390         imx_iomux_v3_setup_multiple_pads(misc_pads,
 391                                          ARRAY_SIZE(misc_pads));
 392
 393 #if defined(CONFIG_VIDEO_IPUV3)
 394         /* Set LDB clock to Video PLL */
 395         select_ldb_di_clock_source(MXC_PLL5_CLK);
 396 #endif
 397         return 0;
 398 }
 399
 400 static void set_confidx(const struct vpd_cache* vpd)
 401 {
 402         switch (vpd->product_id) {
 403         case VPD_PRODUCT_B450:
 404                 confidx = 1;
 405                 break;
 406         case VPD_PRODUCT_B650:
 407                 confidx = 2;
 408                 break;
 409         case VPD_PRODUCT_B850:
 410                 confidx = 3;
 411                 break;
 412         }
 413 }
 414
 415 int board_init(void)
 416 {
 417         if (!read_i2c_vpd(&vpd, vpd_callback)) {
 418                 int ret, rescan;
 419
 420                 vpd.is_read = true;
 421                 set_confidx(&vpd);
 422
 423                 ret = fdtdec_resetup(&rescan);
 424                 if (!ret && rescan) {
 425                         dm_uninit();
 426                         dm_init_and_scan(false);
 427                 }
 428         }
 429
 430         gpio_request(SUS_S3_OUT, "sus_s3_out");
 431         gpio_direction_output(SUS_S3_OUT, 1);
 432
 433         gpio_request(WIFI_EN, "wifi_en");
 434         gpio_direction_output(WIFI_EN, 1);
 435
 436 #if defined(CONFIG_VIDEO_IPUV3)
 437         if (is_b850v3())
 438                 setup_display_b850v3();
 439         else
 440                 setup_display_bx50v3();
 441 #endif
 442
 443         /* address of boot parameters */
 444         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 445
 446         return 0;
 447 }
 448
 449 #ifdef CONFIG_CMD_BMODE
 450 static const struct boot_mode board_boot_modes[] = {
 451         /* 4 bit bus width */
 452         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 453         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 454         {NULL,   0},
 455 };
 456 #endif
 457
 458 void pmic_init(void)
 459 {
 460         struct udevice *reg;
 461         int ret, i;
 462         static const char * const bucks[] = {
 463                 "bcore1",
 464                 "bcore2",
 465                 "bpro",
 466                 "bmem",
 467                 "bio",
 468                 "bperi",
 469         };
 470
 471         for (i = 0; i < ARRAY_SIZE(bucks); i++) {
 472                 ret = regulator_get_by_devname(bucks[i], &reg);
 473                 if (reg < 0) {
 474                         printf("%s(): Unable to get regulator %s: %d\n",
 475                                __func__, bucks[i], ret);
 476                         continue;
 477                 }
 478                 regulator_set_mode(reg, DA9063_BUCKMODE_SYNC);
 479         }
 480 }
 481
 482 int board_late_init(void)
 483 {
 484         process_vpd(&vpd);
 485
 486 #ifdef CONFIG_CMD_BMODE
 487         add_board_boot_modes(board_boot_modes);
 488 #endif
 489
 490         if (is_b850v3())
 491                 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
 492         else
 493                 env_set("videoargs", "video=LVDS-1:1024x768@65");
 494
 495         /* board specific pmic init */
 496         pmic_init();
 497
 498         check_time();
 499
 500         pci_init();
 501
 502         return 0;
 503 }
 504
 505 /*
 506  * Removes the 'eth[0-9]*addr' environment variable with the given index
 507  *
 508  * @param index [in] the index of the eth_device whose variable is to be removed
 509  */
 510 static void remove_ethaddr_env_var(int index)
 511 {
 512         char env_var_name[9];
 513
 514         sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
 515         env_set(env_var_name, NULL);
 516 }
 517
 518 int last_stage_init(void)
 519 {
 520         int i;
 521
 522         /*
 523          * Remove first three ethaddr which may have been created by
 524          * function process_vpd().
 525          */
 526         for (i = 0; i < 3; ++i)
 527                 remove_ethaddr_env_var(i);
 528
 529         return 0;
 530 }
 531
 532 int checkboard(void)
 533 {
 534         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 535         return 0;
 536 }
 537
 538 #ifdef CONFIG_OF_BOARD_SETUP
 539 int ft_board_setup(void *blob, struct bd_info *bd)
 540 {
 541         char *rtc_status = env_get("rtc_status");
 542
 543         fdt_setprop(blob, 0, "ge,boot-ver", version_string,
 544                     strlen(version_string) + 1);
 545
 546         fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
 547                     strlen(rtc_status) + 1);
 548         return 0;
 549 }
 550 #endif
 551
 552 int board_fit_config_name_match(const char *name)
 553 {
 554         if (!vpd.is_read)
 555                 return strcmp(name, "imx6q-bx50v3");
 556
 557         switch (vpd.product_id) {
 558         case VPD_PRODUCT_B450:
 559                 return strcmp(name, "imx6q-b450v3");
 560         case VPD_PRODUCT_B650:
 561                 return strcmp(name, "imx6q-b650v3");
 562         case VPD_PRODUCT_B850:
 563                 return strcmp(name, "imx6q-b850v3");
 564         default:
 565                 return -1;
 566         }
 567 }
 568
 569 int embedded_dtb_select(void)
 570 {
 571         vpd.is_read = false;
 572         return fdtdec_setup();
 573 }