2 * Copyright 2015 Timesys Corporation
3 * Copyright 2015 General Electric Company
4 * Copyright 2012 Freescale Semiconductor, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <linux/errno.h>
15 #include <asm/mach-imx/mxc_i2c.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/video.h>
20 #include <fsl_esdhc.h>
24 #include <asm/arch/mxc_hdmi.h>
25 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
32 #include "../common/ge_common.h"
33 #include "../common/vpd_reader.h"
34 #include "../../../drivers/net/e1000.h"
35 DECLARE_GLOBAL_DATA_PTR;
37 #ifndef CONFIG_SYS_I2C_EEPROM_ADDR
38 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
39 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
42 #ifndef CONFIG_SYS_I2C_EEPROM_BUS
43 #define CONFIG_SYS_I2C_EEPROM_BUS 4
46 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
50 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
52 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
54 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
55 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
56 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
58 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
59 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
61 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
62 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
64 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
65 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
67 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
68 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
70 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
71 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
72 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
74 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
78 gd->ram_size = imx_ddr_size();
83 static iomux_v3_cfg_t const uart3_pads[] = {
84 MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
85 MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
86 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
87 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
90 static iomux_v3_cfg_t const uart4_pads[] = {
91 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
92 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
95 static iomux_v3_cfg_t const enet_pads[] = {
96 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
98 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
99 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
100 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
101 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
102 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
103 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
104 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
105 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
106 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
107 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
108 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
109 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
110 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
111 /* AR8033 PHY Reset */
112 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
115 static void setup_iomux_enet(void)
117 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
119 /* Reset AR8033 PHY */
120 gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
122 gpio_set_value(IMX_GPIO_NR(1, 28), 1);
126 static iomux_v3_cfg_t const usdhc2_pads[] = {
127 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
136 static iomux_v3_cfg_t const usdhc3_pads[] = {
137 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
150 static iomux_v3_cfg_t const usdhc4_pads[] = {
151 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
156 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
157 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
158 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
159 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
160 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
161 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
162 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
165 static iomux_v3_cfg_t const ecspi1_pads[] = {
166 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
167 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
168 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
169 MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
172 static struct i2c_pads_info i2c_pad_info1 = {
174 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
175 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
176 .gp = IMX_GPIO_NR(5, 27)
179 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
180 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
181 .gp = IMX_GPIO_NR(5, 26)
185 static struct i2c_pads_info i2c_pad_info2 = {
187 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
188 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
189 .gp = IMX_GPIO_NR(4, 12)
192 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
193 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
194 .gp = IMX_GPIO_NR(4, 13)
198 static struct i2c_pads_info i2c_pad_info3 = {
200 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
201 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
202 .gp = IMX_GPIO_NR(1, 3)
205 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
206 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
207 .gp = IMX_GPIO_NR(1, 6)
211 #ifdef CONFIG_MXC_SPI
212 int board_spi_cs_gpio(unsigned bus, unsigned cs)
214 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
217 static void setup_spi(void)
219 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
223 static iomux_v3_cfg_t const pcie_pads[] = {
224 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
225 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
228 static void setup_pcie(void)
230 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
233 static void setup_iomux_uart(void)
235 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
236 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
239 #ifdef CONFIG_FSL_ESDHC
240 struct fsl_esdhc_cfg usdhc_cfg[3] = {
246 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
247 #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
249 int board_mmc_getcd(struct mmc *mmc)
251 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
254 switch (cfg->esdhc_base) {
255 case USDHC2_BASE_ADDR:
256 ret = !gpio_get_value(USDHC2_CD_GPIO);
258 case USDHC3_BASE_ADDR:
259 ret = 1; /* eMMC is always present */
261 case USDHC4_BASE_ADDR:
262 ret = !gpio_get_value(USDHC4_CD_GPIO);
269 int board_mmc_init(bd_t *bis)
274 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
277 imx_iomux_v3_setup_multiple_pads(
278 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
279 gpio_direction_input(USDHC2_CD_GPIO);
280 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
283 imx_iomux_v3_setup_multiple_pads(
284 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
285 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
288 imx_iomux_v3_setup_multiple_pads(
289 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
290 gpio_direction_input(USDHC4_CD_GPIO);
291 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
294 printf("Warning: you configured more USDHC controllers\n"
295 "(%d) then supported by the board (%d)\n",
296 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
300 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
309 static int mx6_rgmii_rework(struct phy_device *phydev)
311 /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
312 /* set device address 0x7 */
313 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
314 /* offset 0x8016: CLK_25M Clock Select */
315 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
316 /* enable register write, no post increment, address 0x7 */
317 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
318 /* set to 125 MHz from local PLL source */
319 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
321 /* rgmii tx clock delay enable */
322 /* set debug port address: SerDes Test and System Mode Control */
323 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
324 /* enable rgmii tx clock delay */
325 /* set the reserved bits to avoid board specific voltage peak issue*/
326 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
331 int board_phy_config(struct phy_device *phydev)
333 mx6_rgmii_rework(phydev);
335 if (phydev->drv->config)
336 phydev->drv->config(phydev);
341 #if defined(CONFIG_VIDEO_IPUV3)
342 static iomux_v3_cfg_t const backlight_pads[] = {
343 /* Power for LVDS Display */
344 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
345 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
346 /* Backlight enable for LVDS display */
347 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
348 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
349 /* backlight PWM brightness control */
350 MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
353 static void do_enable_hdmi(struct display_info_t const *dev)
355 imx_enable_hdmi_phy();
358 int board_cfb_skip(void)
360 gpio_direction_output(LVDS_POWER_GP, 1);
365 static int detect_baseboard(struct display_info_t const *dev)
367 if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
368 IS_ENABLED(CONFIG_TARGET_GE_B650V3))
374 struct display_info_t const displays[] = {{
377 .pixfmt = IPU_PIX_FMT_RGB24,
378 .detect = detect_baseboard,
381 .name = "G121X1-L03",
393 .vmode = FB_VMODE_NONINTERLACED
397 .pixfmt = IPU_PIX_FMT_RGB24,
398 .detect = detect_hdmi,
399 .enable = do_enable_hdmi,
413 .vmode = FB_VMODE_NONINTERLACED
415 size_t display_count = ARRAY_SIZE(displays);
417 static void enable_videopll(void)
419 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
420 s32 timeout = 100000;
422 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
424 /* set video pll to 910MHz (24MHz * (37+11/12))
425 * video pll post div to 910/4 = 227.5MHz
427 clrsetbits_le32(&ccm->analog_pll_video,
428 BM_ANADIG_PLL_VIDEO_DIV_SELECT |
429 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
430 BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
431 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0));
433 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
434 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
436 clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
439 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
443 printf("Warning: video pll lock timeout!\n");
445 clrsetbits_le32(&ccm->analog_pll_video,
446 BM_ANADIG_PLL_VIDEO_BYPASS,
447 BM_ANADIG_PLL_VIDEO_ENABLE);
450 static void setup_display_b850v3(void)
452 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
453 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
457 /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
458 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
462 /* Set LDB_DI0 as clock source for IPU_DI0 */
463 clrsetbits_le32(&mxc_ccm->chsccdr,
464 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
465 (CHSCCDR_CLK_SEL_LDB_DI0 <<
466 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
468 /* Turn on IPU LDB DI0 clocks */
469 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
473 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
474 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
475 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
476 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
477 IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
478 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
479 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
480 IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
481 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
482 IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
485 clrbits_le32(&iomux->gpr[3],
486 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
487 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
488 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
491 static void setup_display_bx50v3(void)
493 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
494 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
496 /* When a reset/reboot is performed the display power needs to be turned
497 * off for atleast 500ms. The boot time is ~300ms, we need to wait for
498 * an additional 200ms here. Unfortunately we use external PMIC for
499 * doing the reset, so can not differentiate between POR vs soft reset
503 /* IPU1 DI0 clock is 480/7 = 68.5 MHz */
504 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
506 /* Set LDB_DI0 as clock source for IPU_DI0 */
507 clrsetbits_le32(&mxc_ccm->chsccdr,
508 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
509 (CHSCCDR_CLK_SEL_LDB_DI0 <<
510 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
512 /* Turn on IPU LDB DI0 clocks */
513 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
517 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
518 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
519 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
520 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
521 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
524 clrsetbits_le32(&iomux->gpr[3],
525 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
526 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
527 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
529 /* backlights off until needed */
530 imx_iomux_v3_setup_multiple_pads(backlight_pads,
531 ARRAY_SIZE(backlight_pads));
532 gpio_direction_input(LVDS_POWER_GP);
533 gpio_direction_input(LVDS_BACKLIGHT_GP);
535 #endif /* CONFIG_VIDEO_IPUV3 */
538 * Do not overwrite the console
539 * Use always serial for U-Boot console
541 int overwrite_console(void)
546 #define VPD_TYPE_INVALID 0x00
547 #define VPD_BLOCK_NETWORK 0x20
548 #define VPD_BLOCK_HWID 0x44
549 #define VPD_PRODUCT_B850 1
550 #define VPD_PRODUCT_B650 2
551 #define VPD_PRODUCT_B450 3
552 #define VPD_HAS_MAC1 0x1
553 #define VPD_HAS_MAC2 0x2
554 #define VPD_MAC_ADDRESS_LENGTH 6
559 unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
560 unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
564 * Extracts MAC and product information from the VPD.
566 static int vpd_callback(void *userdata, u8 id, u8 version, u8 type,
567 size_t size, u8 const *data)
569 struct vpd_cache *vpd = (struct vpd_cache *)userdata;
571 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
573 vpd->product_id = data[0];
574 } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
575 type != VPD_TYPE_INVALID) {
577 vpd->has |= VPD_HAS_MAC1;
578 memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
581 vpd->has |= VPD_HAS_MAC2;
582 memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
589 static void process_vpd(struct vpd_cache *vpd)
594 switch (vpd->product_id) {
595 case VPD_PRODUCT_B450:
596 env_set("confidx", "1");
598 case VPD_PRODUCT_B650:
599 env_set("confidx", "2");
601 case VPD_PRODUCT_B850:
602 env_set("confidx", "3");
606 switch (vpd->product_id) {
607 case VPD_PRODUCT_B450:
609 case VPD_PRODUCT_B650:
613 case VPD_PRODUCT_B850:
619 if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
620 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
622 if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
623 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
626 static int read_vpd(uint eeprom_bus)
628 struct vpd_cache vpd;
632 unsigned int current_i2c_bus = i2c_get_bus_num();
634 res = i2c_set_bus_num(eeprom_bus);
638 data = (uint8_t *)malloc(size);
642 res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
643 CONFIG_SYS_I2C_EEPROM_ADDR_LEN, data, size);
646 memset(&vpd, 0, sizeof(vpd));
647 vpd_reader(size, data, &vpd, vpd_callback);
653 i2c_set_bus_num(current_i2c_bus);
657 int board_eth_init(bd_t *bis)
662 e1000_initialize(bis);
664 return cpu_eth_init(bis);
667 static iomux_v3_cfg_t const misc_pads[] = {
668 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
669 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
670 MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
671 MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
672 MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
673 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
674 MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
675 MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL),
677 #define SUS_S3_OUT IMX_GPIO_NR(4, 11)
678 #define WIFI_EN IMX_GPIO_NR(6, 14)
680 int board_early_init_f(void)
682 imx_iomux_v3_setup_multiple_pads(misc_pads,
683 ARRAY_SIZE(misc_pads));
687 #if defined(CONFIG_VIDEO_IPUV3)
688 if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
689 /* Set LDB clock to Video PLL */
690 select_ldb_di_clock_source(MXC_PLL5_CLK);
692 /* Set LDB clock to USB PLL */
693 select_ldb_di_clock_source(MXC_PLL3_SW_CLK);
700 gpio_direction_output(SUS_S3_OUT, 1);
701 gpio_direction_output(WIFI_EN, 1);
702 #if defined(CONFIG_VIDEO_IPUV3)
703 if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
704 setup_display_b850v3();
706 setup_display_bx50v3();
708 /* address of boot parameters */
709 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
711 #ifdef CONFIG_MXC_SPI
714 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
715 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
716 setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
721 #ifdef CONFIG_CMD_BMODE
722 static const struct boot_mode board_boot_modes[] = {
723 /* 4 bit bus width */
724 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
725 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
733 #define DA9063_I2C_ADDR 0x58
734 #define DA9063_REG_BCORE2_CFG 0x9D
735 #define DA9063_REG_BCORE1_CFG 0x9E
736 #define DA9063_REG_BPRO_CFG 0x9F
737 #define DA9063_REG_BIO_CFG 0xA0
738 #define DA9063_REG_BMEM_CFG 0xA1
739 #define DA9063_REG_BPERI_CFG 0xA2
740 #define DA9063_BUCK_MODE_MASK 0xC0
741 #define DA9063_BUCK_MODE_MANUAL 0x00
742 #define DA9063_BUCK_MODE_SLEEP 0x40
743 #define DA9063_BUCK_MODE_SYNC 0x80
744 #define DA9063_BUCK_MODE_AUTO 0xC0
748 i2c_set_bus_num(I2C_PMIC);
750 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
751 val &= ~DA9063_BUCK_MODE_MASK;
752 val |= DA9063_BUCK_MODE_SYNC;
753 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
755 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
756 val &= ~DA9063_BUCK_MODE_MASK;
757 val |= DA9063_BUCK_MODE_SYNC;
758 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
760 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
761 val &= ~DA9063_BUCK_MODE_MASK;
762 val |= DA9063_BUCK_MODE_SYNC;
763 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
765 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
766 val &= ~DA9063_BUCK_MODE_MASK;
767 val |= DA9063_BUCK_MODE_SYNC;
768 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
770 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
771 val &= ~DA9063_BUCK_MODE_MASK;
772 val |= DA9063_BUCK_MODE_SYNC;
773 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
775 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
776 val &= ~DA9063_BUCK_MODE_MASK;
777 val |= DA9063_BUCK_MODE_SYNC;
778 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
781 int board_late_init(void)
783 read_vpd(CONFIG_SYS_I2C_EEPROM_BUS);
785 #ifdef CONFIG_CMD_BMODE
786 add_board_boot_modes(board_boot_modes);
789 /* board specific pmic init */
798 * Removes the 'eth[0-9]*addr' environment variable with the given index
800 * @param index [in] the index of the eth_device whose variable is to be removed
802 static void remove_ethaddr_env_var(int index)
804 char env_var_name[9];
806 sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
807 env_set(env_var_name, NULL);
810 int last_stage_init(void)
815 * Remove first three ethaddr which may have been created by
816 * function process_vpd().
818 for (i = 0; i < 3; ++i)
819 remove_ethaddr_env_var(i);
826 printf("BOARD: %s\n", CONFIG_BOARD_NAME);
830 static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
832 #ifdef CONFIG_VIDEO_IPUV3
833 /* We need at least 200ms between power on and backlight on
834 * as per specifications from CHI MEI */
837 /* enable backlight PWM 1 */
840 /* duty cycle 5000000ns, period: 5000000ns */
841 pwm_config(0, 5000000, 5000000);
843 /* Backlight Power */
844 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
853 bx50_backlight_enable, 1, 1, do_backlight_enable,
854 "enable Bx50 backlight",