1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Timesys Corporation
4 * Copyright 2015 General Electric Company
5 * Copyright 2012 Freescale Semiconductor, Inc.
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
15 #include <linux/delay.h>
16 #include <linux/errno.h>
17 #include <linux/libfdt.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/mach-imx/boot_mode.h>
21 #include <asm/mach-imx/video.h>
23 #include <fsl_esdhc_imx.h>
27 #include <asm/arch/mxc_hdmi.h>
28 #include <asm/arch/crm_regs.h>
30 #include <asm/arch/sys_proto.h>
31 #include <power/regulator.h>
32 #include <power/da9063_pmic.h>
38 #include "../common/ge_rtc.h"
39 #include "../common/vpd_reader.h"
40 #include "../../../drivers/net/e1000.h"
44 DECLARE_GLOBAL_DATA_PTR;
46 #define VPD_PRODUCT_B850 1
47 #define VPD_PRODUCT_B650 2
48 #define VPD_PRODUCT_B450 3
50 static int productid; /* Default to generic. */
51 static struct vpd_cache vpd;
53 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
54 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
59 gd->ram_size = imx_ddr_size();
64 static int mx6_rgmii_rework(struct phy_device *phydev)
66 /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
67 /* set device address 0x7 */
68 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
69 /* offset 0x8016: CLK_25M Clock Select */
70 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
71 /* enable register write, no post increment, address 0x7 */
72 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
73 /* set to 125 MHz from local PLL source */
74 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
76 /* rgmii tx clock delay enable */
77 /* set debug port address: SerDes Test and System Mode Control */
78 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
79 /* enable rgmii tx clock delay */
80 /* set the reserved bits to avoid board specific voltage peak issue*/
81 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
86 int board_phy_config(struct phy_device *phydev)
88 mx6_rgmii_rework(phydev);
90 if (phydev->drv->config)
91 phydev->drv->config(phydev);
96 #if defined(CONFIG_VIDEO_IPUV3)
97 static void do_enable_backlight(struct display_info_t const *dev)
99 struct udevice *panel;
102 ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
104 printf("Could not find panel: %d\n", ret);
108 panel_set_backlight(panel, 100);
109 panel_enable_backlight(panel);
112 static void do_enable_hdmi(struct display_info_t const *dev)
114 imx_enable_hdmi_phy();
117 static int is_b850v3(void)
119 return productid == VPD_PRODUCT_B850;
122 static int detect_lcd(struct display_info_t const *dev)
127 struct display_info_t const displays[] = {{
130 .pixfmt = IPU_PIX_FMT_RGB24,
131 .detect = detect_lcd,
132 .enable = do_enable_backlight,
134 .name = "G121X1-L03",
146 .vmode = FB_VMODE_NONINTERLACED
150 .pixfmt = IPU_PIX_FMT_RGB24,
151 .detect = detect_hdmi,
152 .enable = do_enable_hdmi,
166 .vmode = FB_VMODE_NONINTERLACED
168 size_t display_count = ARRAY_SIZE(displays);
170 static void enable_videopll(void)
172 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
173 s32 timeout = 100000;
175 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
177 /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2)
181 * CS2CDR[LDB_DI0_CLK_SEL]
183 * +----> LDB_DI0_SERIAL_CLK_ROOT
185 * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz
188 clrsetbits_le32(&ccm->analog_pll_video,
189 BM_ANADIG_PLL_VIDEO_DIV_SELECT |
190 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
191 BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
192 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
194 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
195 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
197 clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
200 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
204 printf("Warning: video pll lock timeout!\n");
206 clrsetbits_le32(&ccm->analog_pll_video,
207 BM_ANADIG_PLL_VIDEO_BYPASS,
208 BM_ANADIG_PLL_VIDEO_ENABLE);
211 static void setup_display_b850v3(void)
213 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
214 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
218 /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
219 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
223 /* Set LDB_DI0 as clock source for IPU_DI0 */
224 clrsetbits_le32(&mxc_ccm->chsccdr,
225 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
226 (CHSCCDR_CLK_SEL_LDB_DI0 <<
227 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
229 /* Turn on IPU LDB DI0 clocks */
230 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
234 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
235 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
236 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
237 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
238 IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
239 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
240 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
241 IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
242 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
243 IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
246 clrbits_le32(&iomux->gpr[3],
247 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
248 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
249 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
252 static void setup_display_bx50v3(void)
254 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
255 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
259 /* When a reset/reboot is performed the display power needs to be turned
260 * off for atleast 500ms. The boot time is ~300ms, we need to wait for
261 * an additional 200ms here. Unfortunately we use external PMIC for
262 * doing the reset, so can not differentiate between POR vs soft reset
266 /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
267 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
269 /* Set LDB_DI0 as clock source for IPU_DI0 */
270 clrsetbits_le32(&mxc_ccm->chsccdr,
271 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
272 (CHSCCDR_CLK_SEL_LDB_DI0 <<
273 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
275 /* Turn on IPU LDB DI0 clocks */
276 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
280 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
281 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
282 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
283 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
284 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
287 clrsetbits_le32(&iomux->gpr[3],
288 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
289 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
290 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
292 #endif /* CONFIG_VIDEO_IPUV3 */
295 * Do not overwrite the console
296 * Use always serial for U-Boot console
298 int overwrite_console(void)
303 #define VPD_TYPE_INVALID 0x00
304 #define VPD_BLOCK_NETWORK 0x20
305 #define VPD_BLOCK_HWID 0x44
306 #define VPD_HAS_MAC1 0x1
307 #define VPD_HAS_MAC2 0x2
308 #define VPD_MAC_ADDRESS_LENGTH 6
314 unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
315 unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
319 * Extracts MAC and product information from the VPD.
321 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
322 size_t size, u8 const *data)
324 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
326 vpd->product_id = data[0];
327 } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
328 type != VPD_TYPE_INVALID) {
330 vpd->has |= VPD_HAS_MAC1;
331 memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
334 vpd->has |= VPD_HAS_MAC2;
335 memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
342 static void process_vpd(struct vpd_cache *vpd)
348 printf("VPD wasn't read");
352 if (vpd->has & VPD_HAS_MAC1)
353 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
355 env_set("ethact", "eth0");
357 switch (vpd->product_id) {
358 case VPD_PRODUCT_B450:
359 env_set("confidx", "1");
362 case VPD_PRODUCT_B650:
363 env_set("confidx", "2");
366 case VPD_PRODUCT_B850:
367 env_set("confidx", "3");
372 if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
373 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
376 static iomux_v3_cfg_t const misc_pads[] = {
377 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
378 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
379 MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
380 MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
381 MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
382 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
383 MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
384 MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL),
386 #define SUS_S3_OUT IMX_GPIO_NR(4, 11)
387 #define PWGIN_IN IMX_GPIO_NR(4, 14)
388 #define WIFI_EN IMX_GPIO_NR(6, 14)
390 int board_early_init_f(void)
392 imx_iomux_v3_setup_multiple_pads(misc_pads,
393 ARRAY_SIZE(misc_pads));
395 #if defined(CONFIG_VIDEO_IPUV3)
396 /* Set LDB clock to Video PLL */
397 select_ldb_di_clock_source(MXC_PLL5_CLK);
404 if (!read_i2c_vpd(&vpd, vpd_callback)) {
408 productid = vpd.product_id;
410 ret = fdtdec_resetup(&rescan);
411 if (!ret && rescan) {
413 dm_init_and_scan(false);
417 gpio_request(SUS_S3_OUT, "sus_s3_out");
418 gpio_direction_output(SUS_S3_OUT, 1);
420 gpio_request(PWGIN_IN, "pwgin_in");
421 gpio_direction_input(PWGIN_IN);
423 gpio_request(WIFI_EN, "wifi_en");
424 gpio_direction_output(WIFI_EN, 1);
426 #if defined(CONFIG_VIDEO_IPUV3)
428 setup_display_b850v3();
430 setup_display_bx50v3();
433 /* address of boot parameters */
434 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
439 #ifdef CONFIG_CMD_BMODE
440 static const struct boot_mode board_boot_modes[] = {
441 /* 4 bit bus width */
442 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
443 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
452 static const char * const bucks[] = {
461 for (i = 0; i < ARRAY_SIZE(bucks); i++) {
462 ret = regulator_get_by_devname(bucks[i], ®);
464 printf("%s(): Unable to get regulator %s: %d\n",
465 __func__, bucks[i], ret);
468 regulator_set_mode(reg, DA9063_BUCKMODE_SYNC);
472 static void detect_boot_cause(void)
474 const char *cause = "POR";
477 if (!gpio_get_value(PWGIN_IN))
480 env_set("bootcause", cause);
483 int board_late_init(void)
487 #ifdef CONFIG_CMD_BMODE
488 add_board_boot_modes(board_boot_modes);
492 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
494 env_set("videoargs", "video=LVDS-1:1024x768@65");
498 /* board specific pmic init */
509 * Removes the 'eth[0-9]*addr' environment variable with the given index
511 * @param index [in] the index of the eth_device whose variable is to be removed
513 static void remove_ethaddr_env_var(int index)
515 char env_var_name[9];
517 sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
518 env_set(env_var_name, NULL);
521 int last_stage_init(void)
526 * Remove first three ethaddr which may have been created by
527 * function process_vpd().
529 for (i = 0; i < 3; ++i)
530 remove_ethaddr_env_var(i);
537 printf("BOARD: %s\n", CONFIG_BOARD_NAME);
541 #ifdef CONFIG_OF_BOARD_SETUP
542 int ft_board_setup(void *blob, struct bd_info *bd)
544 char *rtc_status = env_get("rtc_status");
546 fdt_setprop(blob, 0, "ge,boot-ver", version_string,
547 strlen(version_string) + 1);
549 fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
550 strlen(rtc_status) + 1);
555 int board_fit_config_name_match(const char *name)
558 return strcmp(name, "imx6q-bx50v3");
560 switch (vpd.product_id) {
561 case VPD_PRODUCT_B450:
562 return strcmp(name, "imx6q-b450v3");
563 case VPD_PRODUCT_B650:
564 return strcmp(name, "imx6q-b650v3");
565 case VPD_PRODUCT_B850:
566 return strcmp(name, "imx6q-b850v3");
572 int embedded_dtb_select(void)
575 return fdtdec_setup();