board/ge/bx50v3/bx50v3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Timesys Corporation
   4  * Copyright 2015 General Electric Company
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <image.h>
   9 #include <init.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <env.h>
  15 #include <linux/delay.h>
  16 #include <linux/errno.h>
  17 #include <linux/libfdt.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/iomux-v3.h>
  20 #include <asm/mach-imx/boot_mode.h>
  21 #include <asm/mach-imx/video.h>
  22 #include <mmc.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <miiphy.h>
  25 #include <net.h>
  26 #include <netdev.h>
  27 #include <asm/arch/mxc_hdmi.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/io.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include <power/regulator.h>
  32 #include <power/da9063_pmic.h>
  33 #include <input.h>
  34 #include <pwm.h>
  35 #include <version.h>
  36 #include <stdlib.h>
  37 #include <dm/root.h>
  38 #include "../common/ge_rtc.h"
  39 #include "../common/vpd_reader.h"
  40 #include "../../../drivers/net/e1000.h"
  41 #include <pci.h>
  42 #include <panel.h>
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 #define VPD_PRODUCT_B850 1
  47 #define VPD_PRODUCT_B650 2
  48 #define VPD_PRODUCT_B450 3
  49
  50 static int productid;  /* Default to generic. */
  51 static struct vpd_cache vpd;
  52
  53 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  54         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  55         PAD_CTL_HYS)
  56
  57 int dram_init(void)
  58 {
  59         gd->ram_size = imx_ddr_size();
  60
  61         return 0;
  62 }
  63
  64 static int mx6_rgmii_rework(struct phy_device *phydev)
  65 {
  66         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
  67         /* set device address 0x7 */
  68         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  69         /* offset 0x8016: CLK_25M Clock Select */
  70         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  71         /* enable register write, no post increment, address 0x7 */
  72         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  73         /* set to 125 MHz from local PLL source */
  74         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
  75
  76         /* rgmii tx clock delay enable */
  77         /* set debug port address: SerDes Test and System Mode Control */
  78         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  79         /* enable rgmii tx clock delay */
  80         /* set the reserved bits to avoid board specific voltage peak issue*/
  81         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
  82
  83         return 0;
  84 }
  85
  86 int board_phy_config(struct phy_device *phydev)
  87 {
  88         mx6_rgmii_rework(phydev);
  89
  90         if (phydev->drv->config)
  91                 phydev->drv->config(phydev);
  92
  93         return 0;
  94 }
  95
  96 #if defined(CONFIG_VIDEO_IPUV3)
  97 static void do_enable_backlight(struct display_info_t const *dev)
  98 {
  99         struct udevice *panel;
 100         int ret;
 101
 102         ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
 103         if (ret) {
 104                 printf("Could not find panel: %d\n", ret);
 105                 return;
 106         }
 107
 108         panel_set_backlight(panel, 100);
 109         panel_enable_backlight(panel);
 110 }
 111
 112 static void do_enable_hdmi(struct display_info_t const *dev)
 113 {
 114         imx_enable_hdmi_phy();
 115 }
 116
 117 static int is_b850v3(void)
 118 {
 119         return productid == VPD_PRODUCT_B850;
 120 }
 121
 122 static int detect_lcd(struct display_info_t const *dev)
 123 {
 124         return !is_b850v3();
 125 }
 126
 127 struct display_info_t const displays[] = {{
 128         .bus    = -1,
 129         .addr   = -1,
 130         .pixfmt = IPU_PIX_FMT_RGB24,
 131         .detect = detect_lcd,
 132         .enable = do_enable_backlight,
 133         .mode   = {
 134                 .name           = "G121X1-L03",
 135                 .refresh        = 60,
 136                 .xres           = 1024,
 137                 .yres           = 768,
 138                 .pixclock       = 15385,
 139                 .left_margin    = 20,
 140                 .right_margin   = 300,
 141                 .upper_margin   = 30,
 142                 .lower_margin   = 8,
 143                 .hsync_len      = 1,
 144                 .vsync_len      = 1,
 145                 .sync           = FB_SYNC_EXT,
 146                 .vmode          = FB_VMODE_NONINTERLACED
 147 } }, {
 148         .bus    = -1,
 149         .addr   = 3,
 150         .pixfmt = IPU_PIX_FMT_RGB24,
 151         .detect = detect_hdmi,
 152         .enable = do_enable_hdmi,
 153         .mode   = {
 154                 .name           = "HDMI",
 155                 .refresh        = 60,
 156                 .xres           = 1024,
 157                 .yres           = 768,
 158                 .pixclock       = 15385,
 159                 .left_margin    = 220,
 160                 .right_margin   = 40,
 161                 .upper_margin   = 21,
 162                 .lower_margin   = 7,
 163                 .hsync_len      = 60,
 164                 .vsync_len      = 10,
 165                 .sync           = FB_SYNC_EXT,
 166                 .vmode          = FB_VMODE_NONINTERLACED
 167 } } };
 168 size_t display_count = ARRAY_SIZE(displays);
 169
 170 static void enable_videopll(void)
 171 {
 172         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 173         s32 timeout = 100000;
 174
 175         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 176
 177         /* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
 178          *   |
 179          * PLL5
 180          *   |
 181          * CS2CDR[LDB_DI0_CLK_SEL]
 182          *   |
 183          *   +----> LDB_DI0_SERIAL_CLK_ROOT
 184          *   |
 185          *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
 186          */
 187
 188         clrsetbits_le32(&ccm->analog_pll_video,
 189                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 190                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 191                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 192                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 193
 194         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 195         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 196
 197         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 198
 199         while (timeout--)
 200                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 201                         break;
 202
 203         if (timeout < 0)
 204                 printf("Warning: video pll lock timeout!\n");
 205
 206         clrsetbits_le32(&ccm->analog_pll_video,
 207                         BM_ANADIG_PLL_VIDEO_BYPASS,
 208                         BM_ANADIG_PLL_VIDEO_ENABLE);
 209 }
 210
 211 static void setup_display_b850v3(void)
 212 {
 213         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 214         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 215
 216         enable_videopll();
 217
 218         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 219         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 220
 221         imx_setup_hdmi();
 222
 223         /* Set LDB_DI0 as clock source for IPU_DI0 */
 224         clrsetbits_le32(&mxc_ccm->chsccdr,
 225                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 226                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 227                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 228
 229         /* Turn on IPU LDB DI0 clocks */
 230         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 231
 232         enable_ipu_clock();
 233
 234         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 235                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 236                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 237                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 238                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 239                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 240                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 241                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 242                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 243                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 244                &iomux->gpr[2]);
 245
 246         clrbits_le32(&iomux->gpr[3],
 247                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 248                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 249                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 250 }
 251
 252 static void setup_display_bx50v3(void)
 253 {
 254         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 255         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 256
 257         enable_videopll();
 258
 259         /* When a reset/reboot is performed the display power needs to be turned
 260          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 261          * an additional 200ms here. Unfortunately we use external PMIC for
 262          * doing the reset, so can not differentiate between POR vs soft reset
 263          */
 264         mdelay(200);
 265
 266         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 267         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 268
 269         /* Set LDB_DI0 as clock source for IPU_DI0 */
 270         clrsetbits_le32(&mxc_ccm->chsccdr,
 271                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 272                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 273                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 274
 275         /* Turn on IPU LDB DI0 clocks */
 276         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 277
 278         enable_ipu_clock();
 279
 280         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 281                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 282                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 283                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 284                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 285                &iomux->gpr[2]);
 286
 287         clrsetbits_le32(&iomux->gpr[3],
 288                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 289                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 290                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 291 }
 292 #endif /* CONFIG_VIDEO_IPUV3 */
 293
 294 /*
 295  * Do not overwrite the console
 296  * Use always serial for U-Boot console
 297  */
 298 int overwrite_console(void)
 299 {
 300         return 1;
 301 }
 302
 303 #define VPD_TYPE_INVALID 0x00
 304 #define VPD_BLOCK_NETWORK 0x20
 305 #define VPD_BLOCK_HWID 0x44
 306 #define VPD_HAS_MAC1 0x1
 307 #define VPD_HAS_MAC2 0x2
 308 #define VPD_MAC_ADDRESS_LENGTH 6
 309
 310 struct vpd_cache {
 311         bool is_read;
 312         u8 product_id;
 313         u8 has;
 314         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 315         unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
 316 };
 317
 318 /*
 319  * Extracts MAC and product information from the VPD.
 320  */
 321 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
 322                         size_t size, u8 const *data)
 323 {
 324         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 325             size >= 1) {
 326                 vpd->product_id = data[0];
 327         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 328                    type != VPD_TYPE_INVALID) {
 329                 if (size >= 6) {
 330                         vpd->has |= VPD_HAS_MAC1;
 331                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 332                 }
 333                 if (size >= 12) {
 334                         vpd->has |= VPD_HAS_MAC2;
 335                         memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
 336                 }
 337         }
 338
 339         return 0;
 340 }
 341
 342 static void process_vpd(struct vpd_cache *vpd)
 343 {
 344         int fec_index = 0;
 345         int i210_index = -1;
 346
 347         if (!vpd->is_read) {
 348                 printf("VPD wasn't read");
 349                 return;
 350         }
 351
 352         if (vpd->has & VPD_HAS_MAC1)
 353                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 354
 355         env_set("ethact", "eth0");
 356
 357         switch (vpd->product_id) {
 358         case VPD_PRODUCT_B450:
 359                 env_set("confidx", "1");
 360                 i210_index = 1;
 361                 break;
 362         case VPD_PRODUCT_B650:
 363                 env_set("confidx", "2");
 364                 i210_index = 1;
 365                 break;
 366         case VPD_PRODUCT_B850:
 367                 env_set("confidx", "3");
 368                 i210_index = 2;
 369                 break;
 370         }
 371
 372         if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 373                 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 374 }
 375
 376 static iomux_v3_cfg_t const misc_pads[] = {
 377         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 378         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 379         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 380         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 381         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 382         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 383         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 384         MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 385 };
 386 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 387 #define PWGIN_IN        IMX_GPIO_NR(4, 14)
 388 #define WIFI_EN IMX_GPIO_NR(6, 14)
 389
 390 int board_early_init_f(void)
 391 {
 392         imx_iomux_v3_setup_multiple_pads(misc_pads,
 393                                          ARRAY_SIZE(misc_pads));
 394
 395 #if defined(CONFIG_VIDEO_IPUV3)
 396         /* Set LDB clock to Video PLL */
 397         select_ldb_di_clock_source(MXC_PLL5_CLK);
 398 #endif
 399         return 0;
 400 }
 401
 402 int board_init(void)
 403 {
 404         if (!read_i2c_vpd(&vpd, vpd_callback)) {
 405                 int ret, rescan;
 406
 407                 vpd.is_read = true;
 408                 productid = vpd.product_id;
 409
 410                 ret = fdtdec_resetup(&rescan);
 411                 if (!ret && rescan) {
 412                         dm_uninit();
 413                         dm_init_and_scan(false);
 414                 }
 415         }
 416
 417         gpio_request(SUS_S3_OUT, "sus_s3_out");
 418         gpio_direction_output(SUS_S3_OUT, 1);
 419
 420         gpio_request(PWGIN_IN, "pwgin_in");
 421         gpio_direction_input(PWGIN_IN);
 422
 423         gpio_request(WIFI_EN, "wifi_en");
 424         gpio_direction_output(WIFI_EN, 1);
 425
 426 #if defined(CONFIG_VIDEO_IPUV3)
 427         if (is_b850v3())
 428                 setup_display_b850v3();
 429         else
 430                 setup_display_bx50v3();
 431 #endif
 432
 433         /* address of boot parameters */
 434         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 435
 436         return 0;
 437 }
 438
 439 #ifdef CONFIG_CMD_BMODE
 440 static const struct boot_mode board_boot_modes[] = {
 441         /* 4 bit bus width */
 442         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 443         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 444         {NULL,   0},
 445 };
 446 #endif
 447
 448 void pmic_init(void)
 449 {
 450         struct udevice *reg;
 451         int ret, i;
 452         static const char * const bucks[] = {
 453                 "bcore1",
 454                 "bcore2",
 455                 "bpro",
 456                 "bmem",
 457                 "bio",
 458                 "bperi",
 459         };
 460
 461         for (i = 0; i < ARRAY_SIZE(bucks); i++) {
 462                 ret = regulator_get_by_devname(bucks[i], &reg);
 463                 if (reg < 0) {
 464                         printf("%s(): Unable to get regulator %s: %d\n",
 465                                __func__, bucks[i], ret);
 466                         continue;
 467                 }
 468                 regulator_set_mode(reg, DA9063_BUCKMODE_SYNC);
 469         }
 470 }
 471
 472 static void detect_boot_cause(void)
 473 {
 474         const char *cause = "POR";
 475
 476         if (is_b850v3())
 477                 if (!gpio_get_value(PWGIN_IN))
 478                         cause = "PM_WDOG";
 479
 480         env_set("bootcause", cause);
 481 }
 482
 483 int board_late_init(void)
 484 {
 485         process_vpd(&vpd);
 486
 487 #ifdef CONFIG_CMD_BMODE
 488         add_board_boot_modes(board_boot_modes);
 489 #endif
 490
 491         if (is_b850v3())
 492                 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
 493         else
 494                 env_set("videoargs", "video=LVDS-1:1024x768@65");
 495
 496         detect_boot_cause();
 497
 498         /* board specific pmic init */
 499         pmic_init();
 500
 501         check_time();
 502
 503         pci_init();
 504
 505         return 0;
 506 }
 507
 508 /*
 509  * Removes the 'eth[0-9]*addr' environment variable with the given index
 510  *
 511  * @param index [in] the index of the eth_device whose variable is to be removed
 512  */
 513 static void remove_ethaddr_env_var(int index)
 514 {
 515         char env_var_name[9];
 516
 517         sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
 518         env_set(env_var_name, NULL);
 519 }
 520
 521 int last_stage_init(void)
 522 {
 523         int i;
 524
 525         /*
 526          * Remove first three ethaddr which may have been created by
 527          * function process_vpd().
 528          */
 529         for (i = 0; i < 3; ++i)
 530                 remove_ethaddr_env_var(i);
 531
 532         return 0;
 533 }
 534
 535 int checkboard(void)
 536 {
 537         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 538         return 0;
 539 }
 540
 541 #ifdef CONFIG_OF_BOARD_SETUP
 542 int ft_board_setup(void *blob, struct bd_info *bd)
 543 {
 544         char *rtc_status = env_get("rtc_status");
 545
 546         fdt_setprop(blob, 0, "ge,boot-ver", version_string,
 547                     strlen(version_string) + 1);
 548
 549         fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
 550                     strlen(rtc_status) + 1);
 551         return 0;
 552 }
 553 #endif
 554
 555 int board_fit_config_name_match(const char *name)
 556 {
 557         if (!vpd.is_read)
 558                 return strcmp(name, "imx6q-bx50v3");
 559
 560         switch (vpd.product_id) {
 561         case VPD_PRODUCT_B450:
 562                 return strcmp(name, "imx6q-b450v3");
 563         case VPD_PRODUCT_B650:
 564                 return strcmp(name, "imx6q-b650v3");
 565         case VPD_PRODUCT_B850:
 566                 return strcmp(name, "imx6q-b850v3");
 567         default:
 568                 return -1;
 569         }
 570 }
 571
 572 int embedded_dtb_select(void)
 573 {
 574         vpd.is_read = false;
 575         return fdtdec_setup();
 576 }