board/ge/bx50v3/bx50v3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Timesys Corporation
   4  * Copyright 2015 General Electric Company
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/mx6-pins.h>
  12 #include <linux/errno.h>
  13 #include <asm/gpio.h>
  14 #include <asm/mach-imx/mxc_i2c.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/mach-imx/video.h>
  18 #include <mmc.h>
  19 #include <fsl_esdhc.h>
  20 #include <miiphy.h>
  21 #include <net.h>
  22 #include <netdev.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <i2c.h>
  28 #include <input.h>
  29 #include <pwm.h>
  30 #include <stdlib.h>
  31 #include "../common/ge_common.h"
  32 #include "../common/vpd_reader.h"
  33 #include "../../../drivers/net/e1000.h"
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 static int confidx = 3;  /* Default to b850v3. */
  37 static struct vpd_cache vpd;
  38
  39 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  40         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  41         PAD_CTL_HYS)
  42
  43 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  44         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  45         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  46
  47 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  48         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  49
  50 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  51         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  52
  53 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  54         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  55
  56 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  57                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  58
  59 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  61         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  62
  63 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  64
  65 int dram_init(void)
  66 {
  67         gd->ram_size = imx_ddr_size();
  68
  69         return 0;
  70 }
  71
  72 static iomux_v3_cfg_t const uart3_pads[] = {
  73         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  74         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  75         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  76         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  77 };
  78
  79 static iomux_v3_cfg_t const uart4_pads[] = {
  80         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  81         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  82 };
  83
  84 static iomux_v3_cfg_t const enet_pads[] = {
  85         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86         MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  94         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  95         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  96         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  97         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  98         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  99         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 100         /* AR8033 PHY Reset */
 101         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 102 };
 103
 104 static void setup_iomux_enet(void)
 105 {
 106         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 107
 108         /* Reset AR8033 PHY */
 109         gpio_request(IMX_GPIO_NR(1, 28), "fec_rst");
 110         gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
 111         mdelay(10);
 112         gpio_set_value(IMX_GPIO_NR(1, 28), 1);
 113         mdelay(1);
 114 }
 115
 116 static iomux_v3_cfg_t const ecspi1_pads[] = {
 117         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 118         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 119         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 120         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 121 };
 122
 123 static struct i2c_pads_info i2c_pad_info1 = {
 124         .scl = {
 125                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
 126                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
 127                 .gp = IMX_GPIO_NR(5, 27)
 128         },
 129         .sda = {
 130                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
 131                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
 132                 .gp = IMX_GPIO_NR(5, 26)
 133         }
 134 };
 135
 136 static struct i2c_pads_info i2c_pad_info2 = {
 137         .scl = {
 138                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 139                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 140                 .gp = IMX_GPIO_NR(4, 12)
 141         },
 142         .sda = {
 143                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 144                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 145                 .gp = IMX_GPIO_NR(4, 13)
 146         }
 147 };
 148
 149 static struct i2c_pads_info i2c_pad_info3 = {
 150         .scl = {
 151                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
 152                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
 153                 .gp = IMX_GPIO_NR(1, 3)
 154         },
 155         .sda = {
 156                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 157                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 158                 .gp = IMX_GPIO_NR(1, 6)
 159         }
 160 };
 161
 162 #ifdef CONFIG_MXC_SPI
 163 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 164 {
 165         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
 166 }
 167
 168 static void setup_spi(void)
 169 {
 170         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 171 }
 172 #endif
 173
 174 static iomux_v3_cfg_t const pcie_pads[] = {
 175         MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 176         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 177 };
 178
 179 static void setup_pcie(void)
 180 {
 181         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 182 }
 183
 184 static void setup_iomux_uart(void)
 185 {
 186         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 187         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 188 }
 189
 190 static int mx6_rgmii_rework(struct phy_device *phydev)
 191 {
 192         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
 193         /* set device address 0x7 */
 194         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 195         /* offset 0x8016: CLK_25M Clock Select */
 196         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 197         /* enable register write, no post increment, address 0x7 */
 198         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 199         /* set to 125 MHz from local PLL source */
 200         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 201
 202         /* rgmii tx clock delay enable */
 203         /* set debug port address: SerDes Test and System Mode Control */
 204         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 205         /* enable rgmii tx clock delay */
 206         /* set the reserved bits to avoid board specific voltage peak issue*/
 207         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 208
 209         return 0;
 210 }
 211
 212 int board_phy_config(struct phy_device *phydev)
 213 {
 214         mx6_rgmii_rework(phydev);
 215
 216         if (phydev->drv->config)
 217                 phydev->drv->config(phydev);
 218
 219         return 0;
 220 }
 221
 222 #if defined(CONFIG_VIDEO_IPUV3)
 223 static iomux_v3_cfg_t const backlight_pads[] = {
 224         /* Power for LVDS Display */
 225         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 226 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 227         /* Backlight enable for LVDS display */
 228         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 229 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 230         /* backlight PWM brightness control */
 231         MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 232 };
 233
 234 static void do_enable_hdmi(struct display_info_t const *dev)
 235 {
 236         imx_enable_hdmi_phy();
 237 }
 238
 239 int board_cfb_skip(void)
 240 {
 241         gpio_direction_output(LVDS_POWER_GP, 1);
 242
 243         return 0;
 244 }
 245
 246 static int is_b850v3(void)
 247 {
 248         return confidx == 3;
 249 }
 250
 251 static int detect_lcd(struct display_info_t const *dev)
 252 {
 253         return !is_b850v3();
 254 }
 255
 256 struct display_info_t const displays[] = {{
 257         .bus    = -1,
 258         .addr   = -1,
 259         .pixfmt = IPU_PIX_FMT_RGB24,
 260         .detect = detect_lcd,
 261         .enable = NULL,
 262         .mode   = {
 263                 .name           = "G121X1-L03",
 264                 .refresh        = 60,
 265                 .xres           = 1024,
 266                 .yres           = 768,
 267                 .pixclock       = 15385,
 268                 .left_margin    = 20,
 269                 .right_margin   = 300,
 270                 .upper_margin   = 30,
 271                 .lower_margin   = 8,
 272                 .hsync_len      = 1,
 273                 .vsync_len      = 1,
 274                 .sync           = FB_SYNC_EXT,
 275                 .vmode          = FB_VMODE_NONINTERLACED
 276 } }, {
 277         .bus    = -1,
 278         .addr   = 3,
 279         .pixfmt = IPU_PIX_FMT_RGB24,
 280         .detect = detect_hdmi,
 281         .enable = do_enable_hdmi,
 282         .mode   = {
 283                 .name           = "HDMI",
 284                 .refresh        = 60,
 285                 .xres           = 1024,
 286                 .yres           = 768,
 287                 .pixclock       = 15385,
 288                 .left_margin    = 220,
 289                 .right_margin   = 40,
 290                 .upper_margin   = 21,
 291                 .lower_margin   = 7,
 292                 .hsync_len      = 60,
 293                 .vsync_len      = 10,
 294                 .sync           = FB_SYNC_EXT,
 295                 .vmode          = FB_VMODE_NONINTERLACED
 296 } } };
 297 size_t display_count = ARRAY_SIZE(displays);
 298
 299 static void enable_videopll(void)
 300 {
 301         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 302         s32 timeout = 100000;
 303
 304         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 305
 306         /* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
 307          *   |
 308          * PLL5
 309          *   |
 310          * CS2CDR[LDB_DI0_CLK_SEL]
 311          *   |
 312          *   +----> LDB_DI0_SERIAL_CLK_ROOT
 313          *   |
 314          *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
 315          */
 316
 317         clrsetbits_le32(&ccm->analog_pll_video,
 318                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 319                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 320                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 321                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 322
 323         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 324         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 325
 326         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 327
 328         while (timeout--)
 329                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 330                         break;
 331
 332         if (timeout < 0)
 333                 printf("Warning: video pll lock timeout!\n");
 334
 335         clrsetbits_le32(&ccm->analog_pll_video,
 336                         BM_ANADIG_PLL_VIDEO_BYPASS,
 337                         BM_ANADIG_PLL_VIDEO_ENABLE);
 338 }
 339
 340 static void setup_display_b850v3(void)
 341 {
 342         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 343         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 344
 345         enable_videopll();
 346
 347         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 348         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 349
 350         imx_setup_hdmi();
 351
 352         /* Set LDB_DI0 as clock source for IPU_DI0 */
 353         clrsetbits_le32(&mxc_ccm->chsccdr,
 354                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 355                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 356                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 357
 358         /* Turn on IPU LDB DI0 clocks */
 359         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 360
 361         enable_ipu_clock();
 362
 363         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 364                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 365                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 366                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 367                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 368                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 369                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 370                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 371                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 372                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 373                &iomux->gpr[2]);
 374
 375         clrbits_le32(&iomux->gpr[3],
 376                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 377                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 378                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 379 }
 380
 381 static void setup_display_bx50v3(void)
 382 {
 383         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 384         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 385
 386         enable_videopll();
 387
 388         /* When a reset/reboot is performed the display power needs to be turned
 389          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 390          * an additional 200ms here. Unfortunately we use external PMIC for
 391          * doing the reset, so can not differentiate between POR vs soft reset
 392          */
 393         mdelay(200);
 394
 395         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 396         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 397
 398         /* Set LDB_DI0 as clock source for IPU_DI0 */
 399         clrsetbits_le32(&mxc_ccm->chsccdr,
 400                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 401                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 402                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 403
 404         /* Turn on IPU LDB DI0 clocks */
 405         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 406
 407         enable_ipu_clock();
 408
 409         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 410                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 411                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 412                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 413                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 414                &iomux->gpr[2]);
 415
 416         clrsetbits_le32(&iomux->gpr[3],
 417                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 418                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 419                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 420
 421         /* backlights off until needed */
 422         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 423                                          ARRAY_SIZE(backlight_pads));
 424         gpio_request(LVDS_POWER_GP, "lvds_power");
 425         gpio_direction_input(LVDS_POWER_GP);
 426 }
 427 #endif /* CONFIG_VIDEO_IPUV3 */
 428
 429 /*
 430  * Do not overwrite the console
 431  * Use always serial for U-Boot console
 432  */
 433 int overwrite_console(void)
 434 {
 435         return 1;
 436 }
 437
 438 #define VPD_TYPE_INVALID 0x00
 439 #define VPD_BLOCK_NETWORK 0x20
 440 #define VPD_BLOCK_HWID 0x44
 441 #define VPD_PRODUCT_B850 1
 442 #define VPD_PRODUCT_B650 2
 443 #define VPD_PRODUCT_B450 3
 444 #define VPD_HAS_MAC1 0x1
 445 #define VPD_HAS_MAC2 0x2
 446 #define VPD_MAC_ADDRESS_LENGTH 6
 447
 448 struct vpd_cache {
 449         bool is_read;
 450         u8 product_id;
 451         u8 has;
 452         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 453         unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
 454 };
 455
 456 /*
 457  * Extracts MAC and product information from the VPD.
 458  */
 459 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
 460                         size_t size, u8 const *data)
 461 {
 462         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 463             size >= 1) {
 464                 vpd->product_id = data[0];
 465         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 466                    type != VPD_TYPE_INVALID) {
 467                 if (size >= 6) {
 468                         vpd->has |= VPD_HAS_MAC1;
 469                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 470                 }
 471                 if (size >= 12) {
 472                         vpd->has |= VPD_HAS_MAC2;
 473                         memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
 474                 }
 475         }
 476
 477         return 0;
 478 }
 479
 480 static void process_vpd(struct vpd_cache *vpd)
 481 {
 482         int fec_index = -1;
 483         int i210_index = -1;
 484
 485         if (!vpd->is_read) {
 486                 printf("VPD wasn't read");
 487                 return;
 488         }
 489
 490         switch (vpd->product_id) {
 491         case VPD_PRODUCT_B450:
 492                 env_set("confidx", "1");
 493                 i210_index = 0;
 494                 fec_index = 1;
 495                 break;
 496         case VPD_PRODUCT_B650:
 497                 env_set("confidx", "2");
 498                 i210_index = 0;
 499                 fec_index = 1;
 500                 break;
 501         case VPD_PRODUCT_B850:
 502                 env_set("confidx", "3");
 503                 i210_index = 1;
 504                 fec_index = 2;
 505                 break;
 506         }
 507
 508         if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
 509                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 510
 511         if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 512                 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 513 }
 514
 515 int board_eth_init(bd_t *bis)
 516 {
 517         setup_iomux_enet();
 518         setup_pcie();
 519
 520         e1000_initialize(bis);
 521
 522         return cpu_eth_init(bis);
 523 }
 524
 525 static iomux_v3_cfg_t const misc_pads[] = {
 526         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 527         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 528         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 529         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 530         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 531         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 532         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 533         MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 534 };
 535 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 536 #define WIFI_EN IMX_GPIO_NR(6, 14)
 537
 538 int board_early_init_f(void)
 539 {
 540         imx_iomux_v3_setup_multiple_pads(misc_pads,
 541                                          ARRAY_SIZE(misc_pads));
 542
 543         setup_iomux_uart();
 544
 545 #if defined(CONFIG_VIDEO_IPUV3)
 546         /* Set LDB clock to Video PLL */
 547         select_ldb_di_clock_source(MXC_PLL5_CLK);
 548 #endif
 549         return 0;
 550 }
 551
 552 static void set_confidx(const struct vpd_cache* vpd)
 553 {
 554         switch (vpd->product_id) {
 555         case VPD_PRODUCT_B450:
 556                 confidx = 1;
 557                 break;
 558         case VPD_PRODUCT_B650:
 559                 confidx = 2;
 560                 break;
 561         case VPD_PRODUCT_B850:
 562                 confidx = 3;
 563                 break;
 564         }
 565 }
 566
 567 int board_init(void)
 568 {
 569         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 570         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 571         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 572
 573         if (!read_vpd(&vpd, vpd_callback)) {
 574                 vpd.is_read = true;
 575                 set_confidx(&vpd);
 576         }
 577
 578         gpio_request(SUS_S3_OUT, "sus_s3_out");
 579         gpio_direction_output(SUS_S3_OUT, 1);
 580
 581         gpio_request(WIFI_EN, "wifi_en");
 582         gpio_direction_output(WIFI_EN, 1);
 583
 584 #if defined(CONFIG_VIDEO_IPUV3)
 585         if (is_b850v3())
 586                 setup_display_b850v3();
 587         else
 588                 setup_display_bx50v3();
 589
 590         gpio_request(LVDS_BACKLIGHT_GP, "lvds_backlight");
 591         gpio_direction_input(LVDS_BACKLIGHT_GP);
 592 #endif
 593
 594         /* address of boot parameters */
 595         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 596
 597 #ifdef CONFIG_MXC_SPI
 598         setup_spi();
 599 #endif
 600         return 0;
 601 }
 602
 603 #ifdef CONFIG_CMD_BMODE
 604 static const struct boot_mode board_boot_modes[] = {
 605         /* 4 bit bus width */
 606         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 607         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 608         {NULL,   0},
 609 };
 610 #endif
 611
 612 void pmic_init(void)
 613 {
 614 #define I2C_PMIC                0x2
 615 #define DA9063_I2C_ADDR         0x58
 616 #define DA9063_REG_BCORE2_CFG   0x9D
 617 #define DA9063_REG_BCORE1_CFG   0x9E
 618 #define DA9063_REG_BPRO_CFG     0x9F
 619 #define DA9063_REG_BIO_CFG      0xA0
 620 #define DA9063_REG_BMEM_CFG     0xA1
 621 #define DA9063_REG_BPERI_CFG    0xA2
 622 #define DA9063_BUCK_MODE_MASK   0xC0
 623 #define DA9063_BUCK_MODE_MANUAL 0x00
 624 #define DA9063_BUCK_MODE_SLEEP  0x40
 625 #define DA9063_BUCK_MODE_SYNC   0x80
 626 #define DA9063_BUCK_MODE_AUTO   0xC0
 627
 628         uchar val;
 629
 630         i2c_set_bus_num(I2C_PMIC);
 631
 632         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 633         val &= ~DA9063_BUCK_MODE_MASK;
 634         val |= DA9063_BUCK_MODE_SYNC;
 635         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 636
 637         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 638         val &= ~DA9063_BUCK_MODE_MASK;
 639         val |= DA9063_BUCK_MODE_SYNC;
 640         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 641
 642         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 643         val &= ~DA9063_BUCK_MODE_MASK;
 644         val |= DA9063_BUCK_MODE_SYNC;
 645         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 646
 647         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 648         val &= ~DA9063_BUCK_MODE_MASK;
 649         val |= DA9063_BUCK_MODE_SYNC;
 650         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 651
 652         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 653         val &= ~DA9063_BUCK_MODE_MASK;
 654         val |= DA9063_BUCK_MODE_SYNC;
 655         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 656
 657         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 658         val &= ~DA9063_BUCK_MODE_MASK;
 659         val |= DA9063_BUCK_MODE_SYNC;
 660         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 661 }
 662
 663 int board_late_init(void)
 664 {
 665         process_vpd(&vpd);
 666
 667 #ifdef CONFIG_CMD_BMODE
 668         add_board_boot_modes(board_boot_modes);
 669 #endif
 670
 671         if (is_b850v3())
 672                 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
 673         else
 674                 env_set("videoargs", "video=LVDS-1:1024x768@65");
 675
 676         /* board specific pmic init */
 677         pmic_init();
 678
 679         check_time();
 680
 681         return 0;
 682 }
 683
 684 /*
 685  * Removes the 'eth[0-9]*addr' environment variable with the given index
 686  *
 687  * @param index [in] the index of the eth_device whose variable is to be removed
 688  */
 689 static void remove_ethaddr_env_var(int index)
 690 {
 691         char env_var_name[9];
 692
 693         sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
 694         env_set(env_var_name, NULL);
 695 }
 696
 697 int last_stage_init(void)
 698 {
 699         int i;
 700
 701         /*
 702          * Remove first three ethaddr which may have been created by
 703          * function process_vpd().
 704          */
 705         for (i = 0; i < 3; ++i)
 706                 remove_ethaddr_env_var(i);
 707
 708         return 0;
 709 }
 710
 711 int checkboard(void)
 712 {
 713         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 714         return 0;
 715 }
 716
 717 static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 718 {
 719 #ifdef CONFIG_VIDEO_IPUV3
 720         /* We need at least 200ms between power on and backlight on
 721          * as per specifications from CHI MEI */
 722         mdelay(250);
 723
 724         /* enable backlight PWM 1 */
 725         pwm_init(0, 0, 0);
 726
 727         /* duty cycle 5000000ns, period: 5000000ns */
 728         pwm_config(0, 5000000, 5000000);
 729
 730         /* Backlight Power */
 731         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 732
 733         pwm_enable(0);
 734 #endif
 735
 736         return 0;
 737 }
 738
 739 U_BOOT_CMD(
 740        bx50_backlight_enable, 1,      1,      do_backlight_enable,
 741        "enable Bx50 backlight",
 742        ""
 743 );