1 // SPDX-License-Identifier: GPL-2.0+
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
14 #include <linux/delay.h>
15 #include <linux/libfdt.h>
16 #include <fdt_support.h>
19 #include <fsl_esdhc.h>
21 #include <asm/fsl_serdes.h>
22 #include <asm/fsl_mpc83xx_serdes.h>
26 #include <gdsys_fpga.h>
28 #include "../common/adv7611.h"
29 #include "../common/ch7301.h"
30 #include "../common/dp501.h"
31 #include "../common/ioep-fpga.h"
32 #include "../common/mclink.h"
33 #include "../common/osd.h"
34 #include "../common/phy.h"
35 #include "../common/fanctrl.h"
42 #define MAX_MUX_CHANNELS 2
46 MCFPGA_INIT_N = 1 << 1,
47 MCFPGA_PROGRAM_N = 1 << 2,
48 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
49 MCFPGA_RESET_N = 1 << 4,
57 uint mclink_fpgacount;
58 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
63 } strider_fans[] = CONFIG_STRIDER_FANS;
65 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
74 res = mclink_send(fpga - 1, regoff, data);
76 printf("mclink_send reg %02lx data %04x returned %d\n",
86 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
95 if (fpga > mclink_fpgacount)
97 res = mclink_receive(fpga - 1, regoff, data);
99 printf("mclink_receive reg %02lx returned %d\n",
110 char *s = env_get("serial#");
111 bool hw_type_cat = pca9698_get_value(0x20, 18);
115 printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
127 int last_stage_init(void)
132 uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
133 #ifdef CONFIG_STRIDER_CPU
134 uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
136 bool hw_type_cat = pca9698_get_value(0x20, 18);
137 #ifdef CONFIG_STRIDER_CON_DP
138 bool is_dh = pca9698_get_value(0x20, 25);
140 bool ch0_sgmii2_present;
142 /* Turn on Analog Devices ADV7611 */
143 pca9698_direction_output(0x20, 8, 0);
145 /* Turn on Parade DP501 */
146 pca9698_direction_output(0x20, 10, 1);
147 pca9698_direction_output(0x20, 11, 1);
149 ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
151 /* wait for FPGA done, then reset FPGA */
152 for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
154 uchar *mclink_controllers = mclink_controllers_dvi;
156 #ifdef CONFIG_STRIDER_CPU
157 if (i2c_probe(mclink_controllers[k])) {
158 mclink_controllers = mclink_controllers_dp;
159 if (i2c_probe(mclink_controllers[k]))
163 if (i2c_probe(mclink_controllers[k]))
166 while (!(pca953x_get_val(mclink_controllers[k])
170 printf("no done for mclink_controller %d\n", k);
175 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
176 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
178 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
184 struct mii_dev *mdiodev = mdio_alloc();
188 strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
189 mdiodev->read = bb_miiphy_read;
190 mdiodev->write = bb_miiphy_write;
192 retval = mdio_register(mdiodev);
195 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
196 if ((mux_ch == 1) && !ch0_sgmii2_present)
199 setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
203 /* give slave-PLLs and Parade DP501 some time to be up and running */
206 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
207 slaves = mclink_probe();
208 mclink_fpgacount = 0;
210 ioep_fpga_print_info(0);
212 if (!adv7611_probe(0))
213 printf(" Advantiv ADV7611 HDMI Receiver\n");
215 #ifdef CONFIG_STRIDER_CON
216 if (ioep_fpga_has_osd(0))
220 #ifdef CONFIG_STRIDER_CON_DP
221 if (ioep_fpga_has_osd(0)) {
228 #ifdef CONFIG_STRIDER_CPU
229 ch7301_probe(0, false);
230 dp501_probe(0, false);
236 mclink_fpgacount = slaves;
238 #ifdef CONFIG_STRIDER_CPU
239 /* get ADV7611 out of reset, power up DP501, give some time to wakeup */
240 for (k = 1; k <= slaves; ++k)
241 FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
246 for (k = 1; k <= slaves; ++k) {
247 ioep_fpga_print_info(k);
248 #ifdef CONFIG_STRIDER_CON
249 if (ioep_fpga_has_osd(k))
252 #ifdef CONFIG_STRIDER_CON_DP
253 if (ioep_fpga_has_osd(k)) {
259 #ifdef CONFIG_STRIDER_CPU
260 if (!adv7611_probe(k))
261 printf(" Advantiv ADV7611 HDMI Receiver\n");
262 ch7301_probe(k, false);
263 dp501_probe(k, false);
267 struct mii_dev *mdiodev = mdio_alloc();
271 strncpy(mdiodev->name, bb_miiphy_buses[k].name,
273 mdiodev->read = bb_miiphy_read;
274 mdiodev->write = bb_miiphy_write;
276 retval = mdio_register(mdiodev);
279 setup_88e1514(bb_miiphy_buses[k].name, 0);
283 for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
284 i2c_set_bus_num(strider_fans[k].bus);
285 init_fan_controller(strider_fans[k].addr);
292 * provide access to fpga gpios (for I2C bitbang)
293 * (these may look all too simple but make iocon.h much more readable)
295 void fpga_gpio_set(uint bus, int pin)
297 FPGA_SET_REG(bus, gpio.set, pin);
300 void fpga_gpio_clear(uint bus, int pin)
302 FPGA_SET_REG(bus, gpio.clear, pin);
305 int fpga_gpio_get(uint bus, int pin)
309 FPGA_GET_REG(bus, gpio.read, &val);
314 #ifdef CONFIG_STRIDER_CON_DP
315 void fpga_control_set(uint bus, int pin)
319 FPGA_GET_REG(bus, control, &val);
320 FPGA_SET_REG(bus, control, val | pin);
323 void fpga_control_clear(uint bus, int pin)
327 FPGA_GET_REG(bus, control, &val);
328 FPGA_SET_REG(bus, control, val & ~pin);
332 void mpc8308_init(void)
334 pca9698_direction_output(0x20, 26, 1);
337 void mpc8308_set_fpga_reset(uint state)
339 pca9698_set_value(0x20, 26, state ? 0 : 1);
342 void mpc8308_setup_hw(void)
344 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
347 * set "startup-finished"-gpios
349 setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
350 setbits_gpio0_out(BIT(31 - 12));
353 int mpc8308_get_fpga_done(uint fpga)
355 return pca9698_get_value(0x20, 20);
358 #ifdef CONFIG_FSL_ESDHC
359 int board_mmc_init(bd_t *bd)
361 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
362 sysconf83xx_t *sysconf = &immr->sysconf;
364 /* Enable cache snooping in eSDHC system configuration register */
365 out_be32(&sysconf->sdhccr, 0x02000000);
367 return fsl_esdhc_mmc_init(bd);
371 static struct pci_region pcie_regions_0[] = {
373 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
374 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
375 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
376 .flags = PCI_REGION_MEM,
379 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
380 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
381 .size = CONFIG_SYS_PCIE1_IO_SIZE,
382 .flags = PCI_REGION_IO,
386 void pci_init_board(void)
388 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
389 sysconf83xx_t *sysconf = &immr->sysconf;
390 law83xx_t *pcie_law = sysconf->pcielaw;
391 struct pci_region *pcie_reg[] = { pcie_regions_0 };
393 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
394 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
396 /* Deassert the resets in the control register */
397 out_be32(&sysconf->pecr1, 0xE0008000);
400 /* Configure PCI Express Local Access Windows */
401 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
402 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
404 mpc83xx_pcie_init(1, pcie_reg);
407 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
409 info->portwidth = FLASH_CFI_16BIT;
410 info->chipwidth = FLASH_CFI_BY16;
411 info->interface = FLASH_CFI_X16;
415 #if defined(CONFIG_OF_BOARD_SETUP)
416 int ft_board_setup(void *blob, bd_t *bd)
418 ft_cpu_setup(blob, bd);
419 fsl_fdt_fixup_dr_usb(blob, bd);
420 fdt_fixup_esdhc(blob, bd);
427 * FPGA MII bitbang implementation
440 static int mii_dummy_init(struct bb_miiphy_bus *bus)
445 static int mii_mdio_active(struct bb_miiphy_bus *bus)
447 struct fpga_mii *fpga_mii = bus->priv;
450 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
452 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
457 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
459 struct fpga_mii *fpga_mii = bus->priv;
461 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
466 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
468 struct fpga_mii *fpga_mii = bus->priv;
471 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
473 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
480 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
483 struct fpga_mii *fpga_mii = bus->priv;
485 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
487 *v = ((gpio & GPIO_MDIO) != 0);
492 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
494 struct fpga_mii *fpga_mii = bus->priv;
497 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
499 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
504 static int mii_delay(struct bb_miiphy_bus *bus)
511 struct bb_miiphy_bus bb_miiphy_buses[] = {
514 .init = mii_dummy_init,
515 .mdio_active = mii_mdio_active,
516 .mdio_tristate = mii_mdio_tristate,
517 .set_mdio = mii_set_mdio,
518 .get_mdio = mii_get_mdio,
519 .set_mdc = mii_set_mdc,
521 .priv = &fpga_mii[0],
525 .init = mii_dummy_init,
526 .mdio_active = mii_mdio_active,
527 .mdio_tristate = mii_mdio_tristate,
528 .set_mdio = mii_set_mdio,
529 .get_mdio = mii_get_mdio,
530 .set_mdc = mii_set_mdc,
532 .priv = &fpga_mii[1],
536 .init = mii_dummy_init,
537 .mdio_active = mii_mdio_active,
538 .mdio_tristate = mii_mdio_tristate,
539 .set_mdio = mii_set_mdio,
540 .get_mdio = mii_get_mdio,
541 .set_mdc = mii_set_mdc,
543 .priv = &fpga_mii[2],
547 .init = mii_dummy_init,
548 .mdio_active = mii_mdio_active,
549 .mdio_tristate = mii_mdio_tristate,
550 .set_mdio = mii_set_mdio,
551 .get_mdio = mii_get_mdio,
552 .set_mdc = mii_set_mdc,
554 .priv = &fpga_mii[3],
558 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);