3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <fdt_support.h>
16 #include <fsl_esdhc.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_mpc83xx_serdes.h>
23 #include <gdsys_fpga.h>
25 #include "../common/ioep-fpga.h"
26 #include "../common/osd.h"
27 #include "../common/mclink.h"
28 #include "../common/phy.h"
35 DECLARE_GLOBAL_DATA_PTR;
37 #define MAX_MUX_CHANNELS 2
41 MCFPGA_INIT_N = 1 << 1,
42 MCFPGA_PROGRAM_N = 1 << 2,
43 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
44 MCFPGA_RESET_N = 1 << 4,
52 unsigned int mclink_fpgacount;
53 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
55 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
64 res = mclink_send(fpga - 1, regoff, data);
66 printf("mclink_send reg %02lx data %04x returned %d\n",
76 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
85 if (fpga > mclink_fpgacount)
87 res = mclink_receive(fpga - 1, regoff, data);
89 printf("mclink_receive reg %02lx returned %d\n",
100 char *s = getenv("serial#");
101 bool hw_type_cat = pca9698_get_value(0x20, 20);
105 printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
117 int last_stage_init(void)
122 unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
124 bool hw_type_cat = pca9698_get_value(0x20, 20);
125 bool ch0_rgmii2_present = false;
127 FPGA_GET_REG(0, fpga_features, &fpga_features);
129 /* Turn on Parade DP501 */
130 pca9698_direction_output(0x20, 10, 1);
132 ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
134 /* wait for FPGA done, then reset FPGA */
135 for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
136 unsigned int ctr = 0;
138 if (i2c_probe(mclink_controllers[k]))
141 while (!(pca953x_get_val(mclink_controllers[k])
145 printf("no done for mclink_controller %d\n", k);
150 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
151 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
153 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
158 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
160 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
161 if ((mux_ch == 1) && !ch0_rgmii2_present)
164 setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
168 /* give slave-PLLs and Parade DP501 some time to be up and running */
171 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
172 slaves = mclink_probe();
173 mclink_fpgacount = 0;
175 ioep_fpga_print_info(0);
181 mclink_fpgacount = slaves;
183 for (k = 1; k <= slaves; ++k) {
184 FPGA_GET_REG(k, fpga_features, &fpga_features);
186 ioep_fpga_print_info(k);
189 miiphy_register(bb_miiphy_buses[k].name,
190 bb_miiphy_read, bb_miiphy_write);
191 setup_88e1514(bb_miiphy_buses[k].name, 0);
199 * provide access to fpga gpios (for I2C bitbang)
200 * (these may look all too simple but make iocon.h much more readable)
202 void fpga_gpio_set(unsigned int bus, int pin)
204 FPGA_SET_REG(bus, gpio.set, pin);
207 void fpga_gpio_clear(unsigned int bus, int pin)
209 FPGA_SET_REG(bus, gpio.clear, pin);
212 int fpga_gpio_get(unsigned int bus, int pin)
216 FPGA_GET_REG(bus, gpio.read, &val);
221 void mpc8308_init(void)
223 pca9698_direction_output(0x20, 4, 1);
226 void mpc8308_set_fpga_reset(unsigned state)
228 pca9698_set_value(0x20, 4, state ? 0 : 1);
231 void mpc8308_setup_hw(void)
233 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
236 * set "startup-finished"-gpios
238 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
239 setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
242 int mpc8308_get_fpga_done(unsigned fpga)
244 return pca9698_get_value(0x20, 19);
247 #ifdef CONFIG_FSL_ESDHC
248 int board_mmc_init(bd_t *bd)
250 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
251 sysconf83xx_t *sysconf = &immr->sysconf;
253 /* Enable cache snooping in eSDHC system configuration register */
254 out_be32(&sysconf->sdhccr, 0x02000000);
256 return fsl_esdhc_mmc_init(bd);
260 static struct pci_region pcie_regions_0[] = {
262 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
263 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
264 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
265 .flags = PCI_REGION_MEM,
268 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
269 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
270 .size = CONFIG_SYS_PCIE1_IO_SIZE,
271 .flags = PCI_REGION_IO,
275 void pci_init_board(void)
277 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
278 sysconf83xx_t *sysconf = &immr->sysconf;
279 law83xx_t *pcie_law = sysconf->pcielaw;
280 struct pci_region *pcie_reg[] = { pcie_regions_0 };
282 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
283 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
285 /* Deassert the resets in the control register */
286 out_be32(&sysconf->pecr1, 0xE0008000);
289 /* Configure PCI Express Local Access Windows */
290 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
291 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
293 mpc83xx_pcie_init(1, pcie_reg);
296 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
298 info->portwidth = FLASH_CFI_16BIT;
299 info->chipwidth = FLASH_CFI_BY16;
300 info->interface = FLASH_CFI_X16;
304 #if defined(CONFIG_OF_BOARD_SETUP)
305 int ft_board_setup(void *blob, bd_t *bd)
307 ft_cpu_setup(blob, bd);
308 fdt_fixup_dr_usb(blob, bd);
309 fdt_fixup_esdhc(blob, bd);
316 * FPGA MII bitbang implementation
329 static int mii_dummy_init(struct bb_miiphy_bus *bus)
334 static int mii_mdio_active(struct bb_miiphy_bus *bus)
336 struct fpga_mii *fpga_mii = bus->priv;
339 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
341 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
346 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
348 struct fpga_mii *fpga_mii = bus->priv;
350 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
355 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
357 struct fpga_mii *fpga_mii = bus->priv;
360 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
362 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
369 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
372 struct fpga_mii *fpga_mii = bus->priv;
374 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
376 *v = ((gpio & GPIO_MDIO) != 0);
381 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
383 struct fpga_mii *fpga_mii = bus->priv;
386 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
388 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
393 static int mii_delay(struct bb_miiphy_bus *bus)
400 struct bb_miiphy_bus bb_miiphy_buses[] = {
403 .init = mii_dummy_init,
404 .mdio_active = mii_mdio_active,
405 .mdio_tristate = mii_mdio_tristate,
406 .set_mdio = mii_set_mdio,
407 .get_mdio = mii_get_mdio,
408 .set_mdc = mii_set_mdc,
410 .priv = &fpga_mii[0],
414 .init = mii_dummy_init,
415 .mdio_active = mii_mdio_active,
416 .mdio_tristate = mii_mdio_tristate,
417 .set_mdio = mii_set_mdio,
418 .get_mdio = mii_get_mdio,
419 .set_mdc = mii_set_mdc,
421 .priv = &fpga_mii[1],
425 .init = mii_dummy_init,
426 .mdio_active = mii_mdio_active,
427 .mdio_tristate = mii_mdio_tristate,
428 .set_mdio = mii_set_mdio,
429 .get_mdio = mii_get_mdio,
430 .set_mdc = mii_set_mdc,
432 .priv = &fpga_mii[2],
436 .init = mii_dummy_init,
437 .mdio_active = mii_mdio_active,
438 .mdio_tristate = mii_mdio_tristate,
439 .set_mdio = mii_set_mdio,
440 .get_mdio = mii_get_mdio,
441 .set_mdc = mii_set_mdc,
443 .priv = &fpga_mii[3],
447 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
448 sizeof(bb_miiphy_buses[0]);