3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * Based on board/amcc/canyonlands/canyonlands.c
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <fdt_support.h>
30 #include <asm/processor.h>
33 #include <asm/4xx_pcie.h>
36 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
38 DECLARE_GLOBAL_DATA_PTR;
40 #define CONFIG_SYS_BCSR3_PCIE 0x10
42 int board_early_init_f(void)
47 * Setup the interrupt controller polarities, triggers, etc.
49 mtdcr(uic0sr, 0xffffffff); /* clear all */
50 mtdcr(uic0er, 0x00000000); /* disable all */
51 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
52 mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
53 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
54 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
55 mtdcr(uic0sr, 0xffffffff); /* clear all */
57 mtdcr(uic1sr, 0xffffffff); /* clear all */
58 mtdcr(uic1er, 0x00000000); /* disable all */
59 mtdcr(uic1cr, 0x00000000); /* all non-critical */
60 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
61 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
62 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
63 mtdcr(uic1sr, 0xffffffff); /* clear all */
65 mtdcr(uic2sr, 0xffffffff); /* clear all */
66 mtdcr(uic2er, 0x00000000); /* disable all */
67 mtdcr(uic2cr, 0x00000000); /* all non-critical */
68 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
69 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
70 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
71 mtdcr(uic2sr, 0xffffffff); /* clear all */
73 mtdcr(uic3sr, 0xffffffff); /* clear all */
74 mtdcr(uic3er, 0x00000000); /* disable all */
75 mtdcr(uic3cr, 0x00000000); /* all non-critical */
76 mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
77 mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
78 mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
79 mtdcr(uic3sr, 0xffffffff); /* clear all */
82 * Configure PFC (Pin Function Control) registers
86 mtsdr(SDR0_PFC0, 0x00007fff);
87 mtsdr(SDR0_PFC1, 0x00040000);
89 /* Enable PCI host functionality in SDR0_PCI0 */
90 mtsdr(SDR0_PCI0, 0xe0000000);
92 mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
94 /* Setup PLB4-AHB bridge based on the system address map */
95 mtdcr(AHB_TOP, 0x8000004B);
96 mtdcr(AHB_BOT, 0x8000004B);
98 if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
100 * Configure USB-STP pins as alternate and not GPIO
101 * It seems to be neccessary to configure the STP pins as GPIO
102 * input at powerup (perhaps while USB reset is asserted). So
103 * we configure those pins to their "real" function now.
105 gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
106 gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
109 /* Trigger board component reset */
110 out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
111 out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
113 out_le16((void *)CONFIG_SYS_IO_BASE, 0xffbf);
114 out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffbf);
116 out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
117 out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
122 int get_cpu_num(void)
124 int cpu = NA_OR_UNKNOWN_CPU;
131 char *s = getenv("serial#");
133 #ifdef CONFIG_DEVCONCENTER
134 printf("Board: DevCon-Center");
136 printf("Board: CompactCenter");
151 * The bootstrap configuration provides default settings for the pci
152 * inbound map (PIM). But the bootstrap config choices are limited and
153 * may not be sufficient for a given board.
155 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
156 void pci_target_init(struct pci_controller *hose)
161 out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
162 out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
163 out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
164 out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
167 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
168 * strapping options to not support sizes such as 128/256 MB.
170 out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
171 out_le32((void *)PCIX0_PIM0LAH, 0);
172 out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
173 out_le32((void *)PCIX0_BAR0, 0);
176 * Program the board's subsystem id/vendor id
178 out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
179 out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
181 out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
183 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
185 #if defined(CONFIG_PCI)
189 * This routine is called to determine if a pci scan should be
190 * performed. With various hardware environments (especially cPCI and
191 * PPMC) it's insufficient to depend on the state of the arbiter enable
192 * bit in the strap register, or generic host/adapter assumptions.
194 * Rather than hard-code a bad assumption in the general 440 code, the
195 * 440 pci code requires the board to decide at runtime.
197 * Return 0 for adapter mode, non-zero for host (monarch) mode.
199 int is_pci_host(struct pci_controller *hose)
201 /* Board is always configured as host. */
204 #endif /* CONFIG_PCI */
206 int board_early_init_r(void)
209 * CompactCenter has 64MBytes, DevCon-Center 128MBytes of NOR FLASH
210 * (Spansion 29GL512), but the boot EBC mapping only supports a maximum
211 * of 16MBytes (4.ff00.0000 - 4.ffff.ffff).
212 * To solve this problem, the FLASH has to get remapped to another
213 * EBC address which accepts bigger regions:
215 * 0xfn00.0000 -> 4.cn00.0000
218 u32 bxcr_bw = (CONFIG_SYS_FLASH_SIZE == 128 << 20) ?
219 EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB;
221 /* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */
222 mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L
225 | EBC_BXCR_BW_16BIT);
227 /* Remove TLB entry of boot EBC mapping */
228 remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
230 /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
231 program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
232 CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
235 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
236 * 0xfc00.0000 is possible
240 * Clear potential errors resulting from auto-calibration.
241 * If not done, then we could get an interrupt later on when
242 * exceptions are enabled.
244 set_mcsr(get_mcsr());
249 int misc_init_r(void)
256 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
257 * This is board specific, so let's do it here.
259 mfsdr(SDR0_ETH_CFG, eth_cfg);
260 /* disable SGMII mode */
261 eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
262 SDR0_ETH_CFG_SGMII1_ENABLE |
263 SDR0_ETH_CFG_SGMII0_ENABLE);
264 /* Set the for 2 RGMII mode */
265 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
266 eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
267 if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
268 eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
270 eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
271 mtsdr(SDR0_ETH_CFG, eth_cfg);
274 * The AHB Bridge core is held in reset after power-on or reset
277 mfsdr(SDR0_SRST1, sdr0_srst1);
278 sdr0_srst1 &= ~SDR0_SRST1_AHB;
279 mtsdr(SDR0_SRST1, sdr0_srst1);
284 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
285 extern void __ft_board_setup(void *blob, bd_t *bd);
287 void ft_board_setup(void *blob, bd_t *bd)
289 __ft_board_setup(blob, bd);
291 fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
292 "disabled", sizeof("disabled"), 1);
294 fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
295 "disabled", sizeof("disabled"), 1);
297 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */