1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
4 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
12 #include <asm/arch/cpu.h>
13 #include <asm-generic/gpio.h>
15 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
16 #include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
18 #include "keyprogram.h"
19 #include "dt_helpers.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 #define ETH_PHY_CTRL_REG 0
26 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11
27 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
29 #define DB_GP_88F68XX_GPP_OUT_ENA_LOW 0x7fffffff
30 #define DB_GP_88F68XX_GPP_OUT_ENA_MID 0xffffefff
32 #define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
33 #define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x00001000
34 #define DB_GP_88F68XX_GPP_POL_LOW 0x0
35 #define DB_GP_88F68XX_GPP_POL_MID 0x0
38 * Define the DDR layout / topology here in the board file. This will
39 * be used by the DDR3 init code in the SPL U-Boot version to configure
40 * the DDR3 controller.
42 static struct mv_ddr_topology_map ddr_topology_map = {
44 0x1, /* active interfaces */
45 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
51 SPEED_BIN_DDR_1600K, /* speed_bin */
52 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
53 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
54 DDR_FREQ_533, /* frequency */
55 0, 0, /* cas_wl cas_l */
56 MV_DDR_TEMP_LOW} }, /* temperature */
57 BUS_MASK_32BIT, /* Busses mask */
58 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
59 { {0} }, /* raw spd data */
60 {0} /* timing parameters */
64 static struct serdes_map serdes_topology_map[] = {
65 {SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
66 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
67 /* SATA tx polarity is inverted */
68 {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
69 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
70 {DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
71 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
74 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
76 *serdes_map_array = serdes_topology_map;
77 *count = ARRAY_SIZE(serdes_topology_map);
81 void board_pex_config(void)
83 #ifdef CONFIG_SPL_BUILD
85 struct gpio_desc gpio = {};
87 if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
88 /* prepare FPGA reconfiguration */
89 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
90 dm_gpio_set_value(&gpio, 0);
92 /* give lunatic PCIe clock some time to stabilize */
95 /* start FPGA reconfiguration */
96 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
99 /* wait for FPGA done */
100 if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {
101 for (k = 0; k < 20; ++k) {
102 if (dm_gpio_get_value(&gpio)) {
103 printf("FPGA done after %u rounds\n", k);
110 /* disable FPGA reset */
111 if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {
112 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
113 dm_gpio_set_value(&gpio, 1);
116 /* wait for FPGA ready */
117 if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {
118 for (k = 0; k < 2; ++k) {
119 if (!dm_gpio_get_value(&gpio))
127 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
129 return &ddr_topology_map;
132 int board_early_init_f(void)
134 #ifdef CONFIG_SPL_BUILD
136 writel(0x00111111, MVEBU_MPP_BASE + 0x00);
137 writel(0x40040000, MVEBU_MPP_BASE + 0x04);
138 writel(0x00466444, MVEBU_MPP_BASE + 0x08);
139 writel(0x00043300, MVEBU_MPP_BASE + 0x0c);
140 writel(0x44400000, MVEBU_MPP_BASE + 0x10);
141 writel(0x20000334, MVEBU_MPP_BASE + 0x14);
142 writel(0x40000000, MVEBU_MPP_BASE + 0x18);
143 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
145 /* Set GPP Out value */
146 writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
147 writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
149 /* Set GPP Polarity */
150 writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
151 writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
153 /* Set GPP Out Enable */
154 writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
155 writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
163 /* Address of boot parameters */
164 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
169 #ifndef CONFIG_SPL_BUILD
170 void init_host_phys(struct mii_dev *bus)
174 for (k = 0; k < 2; ++k) {
175 struct phy_device *phydev;
177 phydev = phy_find_by_mask(bus, 1 << k,
178 PHY_INTERFACE_MODE_SGMII);
185 int ccdc_eth_init(void)
188 uint octo_phy_mask = 0;
192 /* Init SoC's phys */
193 bus = miiphy_get_dev_by_name("ethernet@34000");
198 bus = miiphy_get_dev_by_name("ethernet@70000");
204 octo_phy_mask = calculate_octo_phy_mask();
206 printf("IHS PHYS: %08x", octo_phy_mask);
208 ret = init_octo_phys(octo_phy_mask);
216 puts("fpga was NULL\n");
220 /* reset all FPGA-QSGMII instances */
221 for (k = 0; k < 80; ++k)
222 writel(1 << 31, get_fpga()->qsgmii_port_state[k]);
226 for (k = 0; k < 80; ++k)
227 writel(0, get_fpga()->qsgmii_port_state[k]);
233 int board_late_init(void)
235 #ifndef CONFIG_SPL_BUILD
241 int board_fix_fdt(void *rw_fdt_blob)
243 struct udevice *bus = NULL;
248 err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus);
251 printf("Could not get I2C bus.\n");
255 for (k = 0x21; k <= 0x26; k++) {
257 "/soc/internal-regs/i2c@11000/pca9698@%02x", k);
259 if (!dm_i2c_simple_probe(bus, k))
260 fdt_disable_by_ofname(rw_fdt_blob, name);
266 int last_stage_init(void)
268 #ifndef CONFIG_SPL_BUILD
271 if (tpm_init() || tpm_startup(TPM_ST_CLEAR) ||
272 tpm_continue_self_test()) {
279 load_and_run_keyprog();