1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
4 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
14 #include <asm/global_data.h>
16 #include <asm/arch/cpu.h>
17 #include <asm-generic/gpio.h>
18 #include <linux/delay.h>
20 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
21 #include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
23 #include "keyprogram.h"
24 #include "dt_helpers.h"
28 DECLARE_GLOBAL_DATA_PTR;
30 #define DB_GP_88F68XX_GPP_OUT_ENA_LOW 0x7fffffff
31 #define DB_GP_88F68XX_GPP_OUT_ENA_MID 0xffffefff
33 #define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
34 #define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x00001000
35 #define DB_GP_88F68XX_GPP_POL_LOW 0x0
36 #define DB_GP_88F68XX_GPP_POL_MID 0x0
38 static int get_tpm(struct udevice **devp)
42 rc = uclass_first_device_err(UCLASS_TPM, devp);
44 printf("Could not find TPM (ret=%d)\n", rc);
45 return CMD_RET_FAILURE;
52 * Define the DDR layout / topology here in the board file. This will
53 * be used by the DDR3 init code in the SPL U-Boot version to configure
54 * the DDR3 controller.
56 static struct mv_ddr_topology_map ddr_topology_map = {
58 0x1, /* active interfaces */
59 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
65 SPEED_BIN_DDR_1600K, /* speed_bin */
66 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
67 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
68 MV_DDR_FREQ_533, /* frequency */
69 0, 0, /* cas_wl cas_l */
70 MV_DDR_TEMP_LOW, /* temperature */
71 MV_DDR_TIM_DEFAULT} }, /* timing */
72 BUS_MASK_32BIT, /* Busses mask */
73 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
74 NOT_COMBINED, /* ddr twin-die combined */
75 { {0} }, /* raw spd data */
76 {0} /* timing parameters */
80 static struct serdes_map serdes_topology_map[] = {
81 {SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
82 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
83 /* SATA tx polarity is inverted */
84 {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
85 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
86 {DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
87 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
90 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
92 *serdes_map_array = serdes_topology_map;
93 *count = ARRAY_SIZE(serdes_topology_map);
97 void board_pex_config(void)
99 #ifdef CONFIG_SPL_BUILD
101 struct gpio_desc gpio = {};
103 if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
104 /* prepare FPGA reconfiguration */
105 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
106 dm_gpio_set_value(&gpio, 0);
108 /* give lunatic PCIe clock some time to stabilize */
111 /* start FPGA reconfiguration */
112 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
115 /* wait for FPGA done */
116 if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {
117 for (k = 0; k < 20; ++k) {
118 if (dm_gpio_get_value(&gpio)) {
119 printf("FPGA done after %u rounds\n", k);
126 /* disable FPGA reset */
127 if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {
128 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
129 dm_gpio_set_value(&gpio, 1);
132 /* wait for FPGA ready */
133 if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {
134 for (k = 0; k < 2; ++k) {
135 if (!dm_gpio_get_value(&gpio))
143 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
145 return &ddr_topology_map;
148 int board_early_init_f(void)
150 #ifdef CONFIG_SPL_BUILD
152 writel(0x00111111, MVEBU_MPP_BASE + 0x00);
153 writel(0x40040000, MVEBU_MPP_BASE + 0x04);
154 writel(0x00466444, MVEBU_MPP_BASE + 0x08);
155 writel(0x00043300, MVEBU_MPP_BASE + 0x0c);
156 writel(0x44400000, MVEBU_MPP_BASE + 0x10);
157 writel(0x20000334, MVEBU_MPP_BASE + 0x14);
158 writel(0x40000000, MVEBU_MPP_BASE + 0x18);
159 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
161 /* Set GPP Out value */
162 writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
163 writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
165 /* Set GPP Polarity */
166 writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
167 writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
169 /* Set GPP Out Enable */
170 writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
171 writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
179 /* Address of boot parameters */
180 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
185 #ifndef CONFIG_SPL_BUILD
186 void init_host_phys(struct mii_dev *bus)
190 for (k = 0; k < 2; ++k) {
191 struct phy_device *phydev;
193 phydev = phy_find_by_mask(bus, 1 << k,
194 PHY_INTERFACE_MODE_SGMII);
201 int ccdc_eth_init(void)
204 uint octo_phy_mask = 0;
208 /* Init SoC's phys */
209 bus = miiphy_get_dev_by_name("ethernet@34000");
214 bus = miiphy_get_dev_by_name("ethernet@70000");
220 octo_phy_mask = calculate_octo_phy_mask();
222 printf("IHS PHYS: %08x", octo_phy_mask);
224 ret = init_octo_phys(octo_phy_mask);
232 puts("fpga was NULL\n");
236 /* reset all FPGA-QSGMII instances */
237 for (k = 0; k < 80; ++k)
238 writel(1 << 31, get_fpga()->qsgmii_port_state[k]);
242 for (k = 0; k < 80; ++k)
243 writel(0, get_fpga()->qsgmii_port_state[k]);
249 int board_late_init(void)
251 #ifndef CONFIG_SPL_BUILD
257 int board_fix_fdt(void *rw_fdt_blob)
259 struct udevice *bus = NULL;
264 err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus);
267 printf("Could not get I2C bus.\n");
271 for (k = 0x21; k <= 0x26; k++) {
273 "/soc/internal-regs/i2c@11000/pca9698@%02x", k);
275 if (!dm_i2c_simple_probe(bus, k))
276 fdt_disable_by_ofname(rw_fdt_blob, name);
282 int last_stage_init(void)
287 #ifndef CONFIG_SPL_BUILD
291 if (ret || tpm_init(tpm) || tpm_startup(tpm, TPM_ST_CLEAR) ||
292 tpm_continue_self_test(tpm)) {
299 load_and_run_keyprog(tpm);