3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
6 * by Stefan Roese, DENX Software Engineering, sr@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/ppc4xx.h>
13 #include <asm/ppc405.h>
15 #include <fdt_support.h>
16 #include <asm/processor.h>
18 #include <asm/errno.h>
19 #include <asm/ppc4xx-gpio.h>
25 #include <gdsys_fpga.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #define PHYREG_CONTROL 0
34 #define PHYREG_PAGE_ADDRESS 22
35 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
36 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
37 #define PHYREG_PG2_MAC_SPECIFIC_STATUS_1 17
38 #define PHYREG_PG2_MAC_SPECIFIC_CONTROL 21
40 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
41 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
42 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
43 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
46 UNITTYPE_CCD_SWITCH = 1,
54 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
56 static inline void blank_string(int size)
60 for (i = 0; i < size; i++)
62 for (i = 0; i < size; i++)
64 for (i = 0; i < size; i++)
69 * Board early initialization function
76 #ifdef CONFIG_ENV_IS_IN_FLASH
77 /* Monitor protection ON by default */
78 flash_protect(FLAG_PROTECT_SET,
79 -CONFIG_SYS_MONITOR_LEN,
87 static void print_fpga_info(unsigned dev)
92 int fpga_state = get_fpga_state(dev);
95 unsigned hardware_version;
96 unsigned feature_channels;
97 unsigned feature_expansion;
99 FPGA_GET_REG(dev, versions, &versions);
100 FPGA_GET_REG(dev, fpga_version, &fpga_version);
101 FPGA_GET_REG(dev, fpga_features, &fpga_features);
103 printf("FPGA%d: ", dev);
104 if (fpga_state & FPGA_STATE_PLATFORM)
107 if (fpga_state & FPGA_STATE_DONE_FAILED) {
108 printf(" done timed out\n");
112 if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
113 printf(" refelectione test failed\n");
117 unit_type = (versions & 0xf000) >> 12;
118 hardware_version = versions & 0x000f;
119 feature_channels = fpga_features & 0x007f;
120 feature_expansion = fpga_features & (1<<15);
123 case UNITTYPE_CCD_SWITCH:
124 printf("CCD-Switch");
128 printf("UnitType %d(not supported)", unit_type);
132 switch (hardware_version) {
134 printf(" HW-Ver 1.00\n");
138 printf(" HW-Ver 1.10\n");
142 printf(" HW-Ver %d(not supported)\n",
147 printf(" FPGA V %d.%02d, features:",
148 fpga_version / 100, fpga_version % 100);
150 printf(" %d channel(s)", feature_channels);
152 printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
157 char *s = getenv("serial#");
159 printf("Board: CATCenter Io64\n");
169 int configure_gbit_phy(char *bus, unsigned char addr)
171 unsigned short value;
174 if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
176 /* switch to powerdown */
177 if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
180 if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
184 if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
186 /* disable SGMII autonegotiation */
187 if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48))
190 if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
192 /* switch from powerdown to normal operation */
193 if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
196 if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
199 /* reset phy so settings take effect */
200 if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140))
206 printf("Error writing to the PHY addr=%02x\n", addr);
210 int verify_gbit_phy(char *bus, unsigned char addr)
212 unsigned short value;
215 if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
217 /* verify SGMII link status */
218 if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value))
220 if (!(value & (1 << 10)))
226 printf("Error writing to the PHY addr=%02x\n", addr);
230 int last_stage_init(void)
235 char str_phys[] = "Setup PHYs -";
236 char str_serdes[] = "Start SERDES blocks";
237 char str_channels[] = "Start FPGA channels";
238 char str_locks[] = "Verify SERDES locks";
239 char str_hicb[] = "Verify HICB status";
240 char str_status[] = "Verify PHY status -";
241 char slash[] = "\\|/-\\|/-";
246 /* setup Gbit PHYs */
250 struct mii_dev *mdiodev = mdio_alloc();
253 strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN);
254 mdiodev->read = bb_miiphy_read;
255 mdiodev->write = bb_miiphy_write;
257 retval = mdio_register(mdiodev);
261 for (k = 0; k < 32; ++k) {
262 configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k);
268 struct mii_dev *mdiodev = mdio_alloc();
271 strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII1_BUSNAME, MDIO_NAME_LEN);
272 mdiodev->read = bb_miiphy_read;
273 mdiodev->write = bb_miiphy_write;
275 retval = mdio_register(mdiodev);
279 for (k = 0; k < 32; ++k) {
280 configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k);
284 blank_string(strlen(str_phys));
286 /* take fpga serdes blocks out of reset */
289 FPGA_SET_REG(0, quad_serdes_reset, 0);
290 FPGA_SET_REG(1, quad_serdes_reset, 0);
291 blank_string(strlen(str_serdes));
293 /* take channels out of reset */
296 for (fpga = 0; fpga < 2; ++fpga) {
297 for (k = 0; k < 32; ++k)
298 FPGA_SET_REG(fpga, ch[k].config_int, 0);
300 blank_string(strlen(str_channels));
302 /* verify channels serdes lock */
305 for (fpga = 0; fpga < 2; ++fpga) {
306 for (k = 0; k < 32; ++k) {
308 FPGA_GET_REG(fpga, ch[k].status_int, &status);
309 if (!(status & (1 << 4))) {
311 printf("fpga %d channel %d: no serdes lock\n",
315 FPGA_SET_REG(fpga, ch[k].status_int, 0);
318 blank_string(strlen(str_locks));
320 /* verify hicb_status */
322 for (fpga = 0; fpga < 2; ++fpga) {
323 for (k = 0; k < 32; ++k) {
325 FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status);
327 printf("fpga %d hicb %d: hicb status %04x\n",
330 FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0);
333 blank_string(strlen(str_hicb));
335 /* verify phy status */
337 for (k = 0; k < 32; ++k) {
338 if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) {
339 printf("verify baseboard phy %d failed\n", k);
345 for (k = 0; k < 32; ++k) {
346 if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) {
347 printf("verify extensionboard phy %d failed\n", k);
353 blank_string(strlen(str_status));
355 printf("Starting 64 channels %s\n", failed ? "failed" : "ok");
360 void gd405ex_init(void)
364 if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
365 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
366 gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
368 pca9698_direction_output(0x22, 39, 1);
372 void gd405ex_set_fpga_reset(unsigned state)
374 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
378 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
379 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
381 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
382 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
385 pca9698_set_value(0x22, 39, state ? 0 : 1);
389 void gd405ex_setup_hw(void)
391 gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0);
392 gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1);
395 int gd405ex_get_fpga_done(unsigned fpga)
397 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
400 return in_le16((void *)LATCH3_BASE)
401 & CONFIG_SYS_FPGA_DONE(fpga);
403 return pca9698_get_value(0x22, fpga ? 9 : 8);