3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/processor.h>
13 #include <asm/ppc4xx-gpio.h>
16 #include <gdsys_fpga.h>
18 #include "../common/osd.h"
19 #include "../common/mclink.h"
27 DECLARE_GLOBAL_DATA_PTR;
29 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
30 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
31 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
33 #define MAX_MUX_CHANNELS 2
36 UNITTYPE_MAIN_SERVER = 0,
37 UNITTYPE_MAIN_USER = 1,
38 UNITTYPE_VIDEO_SERVER = 2,
39 UNITTYPE_VIDEO_USER = 3,
60 COMPRESSION_TYPE1_DELTA = 1,
61 COMPRESSION_TYPE1_TYPE2_DELTA = 3,
82 CARRIER_SPEED_2_5G = 1,
87 MCFPGA_INIT_N = 1 << 1,
88 MCFPGA_PROGRAM_N = 1 << 2,
89 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
90 MCFPGA_RESET_N = 1 << 4,
98 unsigned int mclink_fpgacount;
99 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
101 static int setup_88e1518(const char *bus, unsigned char addr);
103 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
112 res = mclink_send(fpga - 1, regoff, data);
114 printf("mclink_send reg %02lx data %04x returned %d\n",
124 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
130 *data = in_le16(reg);
133 if (fpga > mclink_fpgacount)
135 res = mclink_receive(fpga - 1, regoff, data);
137 printf("mclink_receive reg %02lx returned %d\n",
147 * Check Board Identity:
151 char *s = getenv("serial#");
167 static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
173 unsigned hardware_version;
174 unsigned feature_compression;
175 unsigned feature_osd;
176 unsigned feature_audio;
177 unsigned feature_sysclock;
178 unsigned feature_ramconfig;
179 unsigned feature_carrier_speed;
180 unsigned feature_carriers;
181 unsigned feature_video_channels;
183 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
185 FPGA_GET_REG(0, versions, &versions);
186 FPGA_GET_REG(0, fpga_version, &fpga_version);
187 FPGA_GET_REG(0, fpga_features, &fpga_features);
189 unit_type = (versions & 0xf000) >> 12;
190 feature_compression = (fpga_features & 0xe000) >> 13;
191 feature_osd = fpga_features & (1<<11);
192 feature_audio = (fpga_features & 0x0600) >> 9;
193 feature_sysclock = (fpga_features & 0x0180) >> 7;
194 feature_ramconfig = (fpga_features & 0x0060) >> 5;
195 feature_carrier_speed = fpga_features & (1<<4);
196 feature_carriers = (fpga_features & 0x000c) >> 2;
197 feature_video_channels = fpga_features & 0x0003;
203 case UNITTYPE_MAIN_USER:
204 printf("Mainchannel");
207 case UNITTYPE_VIDEO_USER:
208 printf("Videochannel");
212 printf("UnitType %d(not supported)", unit_type);
216 if (unit_type == UNITTYPE_MAIN_USER) {
219 (in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
222 (!!pca9698_get_value(0x20, 24) << 0)
223 | (!!pca9698_get_value(0x20, 25) << 1)
224 | (!!pca9698_get_value(0x20, 26) << 2)
225 | (!!pca9698_get_value(0x20, 27) << 3);
226 switch (hardware_version) {
228 printf(" HW-Ver 1.00,");
232 printf(" HW-Ver 1.04,");
236 printf(" HW-Ver 1.10,");
240 printf(" HW-Ver 1.20-1.21,");
244 printf(" HW-Ver 2.00,");
248 printf(" HW-Ver 2.10,");
252 printf(" HW-Ver 2.20,");
256 printf(" HW-Ver 2.30,");
260 printf(" HW-Ver %d(not supported),",
268 if (unit_type == UNITTYPE_VIDEO_USER) {
269 hardware_version = versions & 0x000f;
270 switch (hardware_version) {
272 printf(" HW-Ver 2.00,");
276 printf(" HW-Ver 2.10,");
280 printf(" HW-Ver %d(not supported),",
286 printf(" FPGA V %d.%02d\n features:",
287 fpga_version / 100, fpga_version % 100);
290 switch (feature_compression) {
291 case COMPRESSION_NONE:
292 printf(" no compression");
295 case COMPRESSION_TYPE1_DELTA:
296 printf(" type1-deltacompression");
299 case COMPRESSION_TYPE1_TYPE2_DELTA:
300 printf(" type1-deltacompression, type2-inlinecompression");
304 printf(" compression %d(not supported)", feature_compression);
308 printf(", %sosd", feature_osd ? "" : "no ");
310 switch (feature_audio) {
312 printf(", no audio");
316 printf(", audio tx");
320 printf(", audio rx");
324 printf(", audio rx+tx");
328 printf(", audio %d(not supported)", feature_audio);
334 switch (feature_sysclock) {
336 printf("clock 147.456 MHz");
340 printf("clock %d(not supported)", feature_sysclock);
344 switch (feature_ramconfig) {
346 printf(", RAM 32 bit DDR2");
350 printf(", RAM 32 bit DDR3");
354 printf(", RAM %d(not supported)", feature_ramconfig);
358 printf(", %d carrier(s) %s", feature_carriers,
359 feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
361 printf(", %d video channel(s)\n", feature_video_channels);
364 int last_stage_init(void)
369 unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
370 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
372 int feature_carrier_speed = fpga_features & (1<<4);
373 bool ch0_rgmii2_present = false;
375 FPGA_GET_REG(0, fpga_features, &fpga_features);
378 ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
380 print_fpga_info(0, ch0_rgmii2_present);
383 /* wait for FPGA done */
384 for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
385 unsigned int ctr = 0;
387 if (i2c_probe(mclink_controllers[k]))
390 while (!(pca953x_get_val(mclink_controllers[k])
394 printf("no done for mclink_controller %d\n", k);
400 if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
401 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
403 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
404 if ((mux_ch == 1) && !ch0_rgmii2_present)
407 setup_88e1518(bb_miiphy_buses[0].name, mux_ch);
411 /* wait for slave-PLLs to be up and running */
414 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
415 slaves = mclink_probe();
416 mclink_fpgacount = 0;
421 mclink_fpgacount = slaves;
423 for (k = 1; k <= slaves; ++k) {
424 FPGA_GET_REG(k, fpga_features, &fpga_features);
425 feature_carrier_speed = fpga_features & (1<<4);
427 print_fpga_info(k, false);
429 if (feature_carrier_speed == CARRIER_SPEED_1G) {
430 miiphy_register(bb_miiphy_buses[k].name,
431 bb_miiphy_read, bb_miiphy_write);
432 setup_88e1518(bb_miiphy_buses[k].name, 0);
440 * provide access to fpga gpios (for I2C bitbang)
441 * (these may look all too simple but make iocon.h much more readable)
443 void fpga_gpio_set(unsigned int bus, int pin)
445 FPGA_SET_REG(bus, gpio.set, pin);
448 void fpga_gpio_clear(unsigned int bus, int pin)
450 FPGA_SET_REG(bus, gpio.clear, pin);
453 int fpga_gpio_get(unsigned int bus, int pin)
457 FPGA_GET_REG(bus, gpio.read, &val);
462 void gd405ep_init(void)
466 if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
467 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
468 gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
470 pca9698_direction_output(0x20, 4, 1);
474 void gd405ep_set_fpga_reset(unsigned state)
476 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
480 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
481 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
483 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
484 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
487 pca9698_set_value(0x20, 4, state ? 0 : 1);
491 void gd405ep_setup_hw(void)
494 * set "startup-finished"-gpios
496 gpio_write_bit(21, 0);
497 gpio_write_bit(22, 1);
500 int gd405ep_get_fpga_done(unsigned fpga)
502 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
505 return in_le16((void *)LATCH2_BASE)
506 & CONFIG_SYS_FPGA_DONE(fpga);
508 return pca9698_get_value(0x20, 20);
512 * FPGA MII bitbang implementation
525 static int mii_dummy_init(struct bb_miiphy_bus *bus)
530 static int mii_mdio_active(struct bb_miiphy_bus *bus)
532 struct fpga_mii *fpga_mii = bus->priv;
535 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
537 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
542 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
544 struct fpga_mii *fpga_mii = bus->priv;
546 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
551 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
553 struct fpga_mii *fpga_mii = bus->priv;
556 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
558 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
565 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
568 struct fpga_mii *fpga_mii = bus->priv;
570 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
572 *v = ((gpio & GPIO_MDIO) != 0);
577 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
579 struct fpga_mii *fpga_mii = bus->priv;
582 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
584 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
589 static int mii_delay(struct bb_miiphy_bus *bus)
596 struct bb_miiphy_bus bb_miiphy_buses[] = {
599 .init = mii_dummy_init,
600 .mdio_active = mii_mdio_active,
601 .mdio_tristate = mii_mdio_tristate,
602 .set_mdio = mii_set_mdio,
603 .get_mdio = mii_get_mdio,
604 .set_mdc = mii_set_mdc,
606 .priv = &fpga_mii[0],
610 .init = mii_dummy_init,
611 .mdio_active = mii_mdio_active,
612 .mdio_tristate = mii_mdio_tristate,
613 .set_mdio = mii_set_mdio,
614 .get_mdio = mii_get_mdio,
615 .set_mdc = mii_set_mdc,
617 .priv = &fpga_mii[1],
621 .init = mii_dummy_init,
622 .mdio_active = mii_mdio_active,
623 .mdio_tristate = mii_mdio_tristate,
624 .set_mdio = mii_set_mdio,
625 .get_mdio = mii_get_mdio,
626 .set_mdc = mii_set_mdc,
628 .priv = &fpga_mii[2],
632 .init = mii_dummy_init,
633 .mdio_active = mii_mdio_active,
634 .mdio_tristate = mii_mdio_tristate,
635 .set_mdio = mii_set_mdio,
636 .get_mdio = mii_get_mdio,
637 .set_mdc = mii_set_mdc,
639 .priv = &fpga_mii[3],
643 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
644 sizeof(bb_miiphy_buses[0]);
650 MIICMD_WAIT_FOR_VALUE,
653 struct mii_setupcmd {
662 * verify we are talking to a 88e1518
664 struct mii_setupcmd verify_88e1518[] = {
665 { MIICMD_SET, 22, 0x0000 },
666 { MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff },
667 { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 },
671 * workaround for erratum mentioned in 88E1518 release notes
673 struct mii_setupcmd fixup_88e1518[] = {
674 { MIICMD_SET, 22, 0x00ff },
675 { MIICMD_SET, 17, 0x214b },
676 { MIICMD_SET, 16, 0x2144 },
677 { MIICMD_SET, 17, 0x0c28 },
678 { MIICMD_SET, 16, 0x2146 },
679 { MIICMD_SET, 17, 0xb233 },
680 { MIICMD_SET, 16, 0x214d },
681 { MIICMD_SET, 17, 0xcc0c },
682 { MIICMD_SET, 16, 0x2159 },
683 { MIICMD_SET, 22, 0x00fb },
684 { MIICMD_SET, 7, 0xc00d },
685 { MIICMD_SET, 22, 0x0000 },
689 * default initialization:
690 * - set RGMII receive timing to "receive clock transition when data stable"
691 * - set RGMII transmit timing to "transmit clock internally delayed"
692 * - set RGMII output impedance target to 78,8 Ohm
693 * - run output impedance calibration
694 * - set autonegotiation advertise to 1000FD only
696 struct mii_setupcmd default_88e1518[] = {
697 { MIICMD_SET, 22, 0x0002 },
698 { MIICMD_MODIFY, 21, 0x0030, 0x0030 },
699 { MIICMD_MODIFY, 25, 0x0000, 0x0003 },
700 { MIICMD_MODIFY, 24, 0x8000, 0x8000 },
701 { MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 },
702 { MIICMD_SET, 22, 0x0000 },
703 { MIICMD_MODIFY, 4, 0x0000, 0x01e0 },
704 { MIICMD_MODIFY, 9, 0x0200, 0x0300 },
708 * turn off CLK125 for PHY daughterboard
710 struct mii_setupcmd ch1fix_88e1518[] = {
711 { MIICMD_SET, 22, 0x0002 },
712 { MIICMD_MODIFY, 16, 0x0006, 0x0006 },
713 { MIICMD_SET, 22, 0x0000 },
717 * perform copper software reset
719 struct mii_setupcmd swreset_88e1518[] = {
720 { MIICMD_SET, 22, 0x0000 },
721 { MIICMD_MODIFY, 0, 0x8000, 0x8000 },
722 { MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 },
725 static int process_setupcmd(const char *bus, unsigned char addr,
726 struct mii_setupcmd *setupcmd)
729 u8 reg = setupcmd->reg;
730 u16 data = setupcmd->data;
731 u16 mask = setupcmd->mask;
732 u32 timeout = setupcmd->timeout;
736 debug("mii %s:%u reg %2u ", bus, addr, reg);
738 switch (setupcmd->token) {
740 res = miiphy_read(bus, addr, reg, &orig_data);
743 debug("is %04x. (value %04x mask %04x) ", orig_data, data,
745 data = (orig_data & ~mask) | (data & mask);
747 debug("=> %04x\n", data);
748 res = miiphy_write(bus, addr, reg, data);
750 case MIICMD_VERIFY_VALUE:
751 res = miiphy_read(bus, addr, reg, &orig_data);
754 if ((orig_data & mask) != (data & mask))
756 debug("(value %04x mask %04x) == %04x? %s\n", data, mask,
757 orig_data, res ? "FAIL" : "PASS");
759 case MIICMD_WAIT_FOR_VALUE:
761 start = get_timer(0);
762 while ((res != 0) && (get_timer(start) < timeout)) {
763 res = miiphy_read(bus, addr, reg, &orig_data);
766 if ((orig_data & mask) != (data & mask))
769 debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data,
770 mask, orig_data, res ? "FAIL" : "PASS",
781 static int process_setup(const char *bus, unsigned char addr,
782 struct mii_setupcmd *setupcmd, unsigned int count)
787 for (k = 0; k < count; ++k) {
788 res = process_setupcmd(bus, addr, &setupcmd[k]);
790 printf("mii cmd %u on bus %s addr %u failed, aborting setup",
791 setupcmd[k].token, bus, addr);
799 static int setup_88e1518(const char *bus, unsigned char addr)
803 res = process_setup(bus, addr,
804 verify_88e1518, ARRAY_SIZE(verify_88e1518));
808 res = process_setup(bus, addr,
809 fixup_88e1518, ARRAY_SIZE(fixup_88e1518));
813 res = process_setup(bus, addr,
814 default_88e1518, ARRAY_SIZE(default_88e1518));
819 res = process_setup(bus, addr,
820 ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518));
825 res = process_setup(bus, addr,
826 swreset_88e1518, ARRAY_SIZE(swreset_88e1518));