board/gdsys/405ep/iocon.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <errno.h>
  11 #include <asm/processor.h>
  12 #include <asm/io.h>
  13 #include <asm/ppc4xx-gpio.h>
  14
  15 #include "405ep.h"
  16 #include <gdsys_fpga.h>
  17
  18 #include "../common/osd.h"
  19 #include "../common/mclink.h"
  20
  21 #include <i2c.h>
  22 #include <pca953x.h>
  23 #include <pca9698.h>
  24
  25 #include <miiphy.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  30 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  31 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  32
  33 enum {
  34         UNITTYPE_MAIN_SERVER = 0,
  35         UNITTYPE_MAIN_USER = 1,
  36         UNITTYPE_VIDEO_SERVER = 2,
  37         UNITTYPE_VIDEO_USER = 3,
  38 };
  39
  40 enum {
  41         HWVER_100 = 0,
  42         HWVER_104 = 1,
  43         HWVER_110 = 2,
  44         HWVER_120 = 3,
  45         HWVER_200 = 4,
  46         HWVER_210 = 5,
  47         HWVER_220 = 6,
  48         HWVER_230 = 7,
  49 };
  50
  51 enum {
  52         FPGA_HWVER_200 = 0,
  53         FPGA_HWVER_210 = 1,
  54 };
  55
  56 enum {
  57         COMPRESSION_NONE = 0,
  58         COMPRESSION_TYPE1_DELTA = 1,
  59         COMPRESSION_TYPE1_TYPE2_DELTA = 3,
  60 };
  61
  62 enum {
  63         AUDIO_NONE = 0,
  64         AUDIO_TX = 1,
  65         AUDIO_RX = 2,
  66         AUDIO_RXTX = 3,
  67 };
  68
  69 enum {
  70         SYSCLK_147456 = 0,
  71 };
  72
  73 enum {
  74         RAM_DDR2_32 = 0,
  75         RAM_DDR3_32 = 1,
  76 };
  77
  78 enum {
  79         CARRIER_SPEED_1G = 0,
  80         CARRIER_SPEED_2_5G = 1,
  81 };
  82
  83 enum {
  84         MCFPGA_DONE = 1 << 0,
  85         MCFPGA_INIT_N = 1 << 1,
  86         MCFPGA_PROGRAM_N = 1 << 2,
  87         MCFPGA_UPDATE_ENABLE_N = 1 << 3,
  88         MCFPGA_RESET_N = 1 << 4,
  89 };
  90
  91 enum {
  92         GPIO_MDC = 1 << 14,
  93         GPIO_MDIO = 1 << 15,
  94 };
  95
  96 unsigned int mclink_fpgacount;
  97 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  98
  99 static int setup_88e1518(const char *bus, unsigned char addr);
 100 static int verify_88e1518(const char *bus, unsigned char addr);
 101
 102 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
 103 {
 104         int res;
 105
 106         switch (fpga) {
 107         case 0:
 108                 out_le16(reg, data);
 109                 break;
 110         default:
 111                 res = mclink_send(fpga - 1, regoff, data);
 112                 if (res < 0) {
 113                         printf("mclink_send reg %02lx data %04x returned %d\n",
 114                                regoff, data, res);
 115                         return res;
 116                 }
 117                 break;
 118         }
 119
 120         return 0;
 121 }
 122
 123 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
 124 {
 125         int res;
 126
 127         switch (fpga) {
 128         case 0:
 129                 *data = in_le16(reg);
 130                 break;
 131         default:
 132                 if (fpga > mclink_fpgacount)
 133                         return -EINVAL;
 134                 res = mclink_receive(fpga - 1, regoff, data);
 135                 if (res < 0) {
 136                         printf("mclink_receive reg %02lx returned %d\n",
 137                                regoff, res);
 138                         return res;
 139                 }
 140         }
 141
 142         return 0;
 143 }
 144
 145 /*
 146  * Check Board Identity:
 147  */
 148 int checkboard(void)
 149 {
 150         char *s = getenv("serial#");
 151
 152         puts("Board: ");
 153
 154         puts("IoCon");
 155
 156         if (s != NULL) {
 157                 puts(", serial# ");
 158                 puts(s);
 159         }
 160
 161         puts("\n");
 162
 163         return 0;
 164 }
 165
 166 static void print_fpga_info(unsigned int fpga)
 167 {
 168         u16 versions;
 169         u16 fpga_version;
 170         u16 fpga_features;
 171         unsigned unit_type;
 172         unsigned hardware_version;
 173         unsigned feature_compression;
 174         unsigned feature_osd;
 175         unsigned feature_audio;
 176         unsigned feature_sysclock;
 177         unsigned feature_ramconfig;
 178         unsigned feature_carrier_speed;
 179         unsigned feature_carriers;
 180         unsigned feature_video_channels;
 181
 182         int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
 183
 184         FPGA_GET_REG(0, versions, &versions);
 185         FPGA_GET_REG(0, fpga_version, &fpga_version);
 186         FPGA_GET_REG(0, fpga_features, &fpga_features);
 187
 188         unit_type = (versions & 0xf000) >> 12;
 189         feature_compression = (fpga_features & 0xe000) >> 13;
 190         feature_osd = fpga_features & (1<<11);
 191         feature_audio = (fpga_features & 0x0600) >> 9;
 192         feature_sysclock = (fpga_features & 0x0180) >> 7;
 193         feature_ramconfig = (fpga_features & 0x0060) >> 5;
 194         feature_carrier_speed = fpga_features & (1<<4);
 195         feature_carriers = (fpga_features & 0x000c) >> 2;
 196         feature_video_channels = fpga_features & 0x0003;
 197
 198         if (legacy)
 199                 printf("legacy ");
 200
 201         switch (unit_type) {
 202         case UNITTYPE_MAIN_USER:
 203                 printf("Mainchannel");
 204                 break;
 205
 206         case UNITTYPE_VIDEO_USER:
 207                 printf("Videochannel");
 208                 break;
 209
 210         default:
 211                 printf("UnitType %d(not supported)", unit_type);
 212                 break;
 213         }
 214
 215         if (unit_type == UNITTYPE_MAIN_USER) {
 216                 if (legacy)
 217                         hardware_version =
 218                                 (in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
 219                 else
 220                         hardware_version =
 221                                   (!!pca9698_get_value(0x20, 24) << 0)
 222                                 | (!!pca9698_get_value(0x20, 25) << 1)
 223                                 | (!!pca9698_get_value(0x20, 26) << 2)
 224                                 | (!!pca9698_get_value(0x20, 27) << 3);
 225                 switch (hardware_version) {
 226                 case HWVER_100:
 227                         printf(" HW-Ver 1.00,");
 228                         break;
 229
 230                 case HWVER_104:
 231                         printf(" HW-Ver 1.04,");
 232                         break;
 233
 234                 case HWVER_110:
 235                         printf(" HW-Ver 1.10,");
 236                         break;
 237
 238                 case HWVER_120:
 239                         printf(" HW-Ver 1.20-1.21,");
 240                         break;
 241
 242                 case HWVER_200:
 243                         printf(" HW-Ver 2.00,");
 244                         break;
 245
 246                 case HWVER_210:
 247                         printf(" HW-Ver 2.10,");
 248                         break;
 249
 250                 case HWVER_220:
 251                         printf(" HW-Ver 2.20,");
 252                         break;
 253
 254                 case HWVER_230:
 255                         printf(" HW-Ver 2.30,");
 256                         break;
 257
 258                 default:
 259                         printf(" HW-Ver %d(not supported),",
 260                                hardware_version);
 261                         break;
 262                 }
 263         }
 264
 265         if (unit_type == UNITTYPE_VIDEO_USER) {
 266                 hardware_version = versions & 0x000f;
 267                 switch (hardware_version) {
 268                 case FPGA_HWVER_200:
 269                         printf(" HW-Ver 2.00,");
 270                         break;
 271
 272                 case FPGA_HWVER_210:
 273                         printf(" HW-Ver 2.10,");
 274                         break;
 275
 276                 default:
 277                         printf(" HW-Ver %d(not supported),",
 278                                hardware_version);
 279                         break;
 280                 }
 281         }
 282
 283         printf(" FPGA V %d.%02d\n       features:",
 284                fpga_version / 100, fpga_version % 100);
 285
 286
 287         switch (feature_compression) {
 288         case COMPRESSION_NONE:
 289                 printf(" no compression");
 290                 break;
 291
 292         case COMPRESSION_TYPE1_DELTA:
 293                 printf(" type1-deltacompression");
 294                 break;
 295
 296         case COMPRESSION_TYPE1_TYPE2_DELTA:
 297                 printf(" type1-deltacompression, type2-inlinecompression");
 298                 break;
 299
 300         default:
 301                 printf(" compression %d(not supported)", feature_compression);
 302                 break;
 303         }
 304
 305         printf(", %sosd", feature_osd ? "" : "no ");
 306
 307         switch (feature_audio) {
 308         case AUDIO_NONE:
 309                 printf(", no audio");
 310                 break;
 311
 312         case AUDIO_TX:
 313                 printf(", audio tx");
 314                 break;
 315
 316         case AUDIO_RX:
 317                 printf(", audio rx");
 318                 break;
 319
 320         case AUDIO_RXTX:
 321                 printf(", audio rx+tx");
 322                 break;
 323
 324         default:
 325                 printf(", audio %d(not supported)", feature_audio);
 326                 break;
 327         }
 328
 329         puts(",\n       ");
 330
 331         switch (feature_sysclock) {
 332         case SYSCLK_147456:
 333                 printf("clock 147.456 MHz");
 334                 break;
 335
 336         default:
 337                 printf("clock %d(not supported)", feature_sysclock);
 338                 break;
 339         }
 340
 341         switch (feature_ramconfig) {
 342         case RAM_DDR2_32:
 343                 printf(", RAM 32 bit DDR2");
 344                 break;
 345
 346         case RAM_DDR3_32:
 347                 printf(", RAM 32 bit DDR3");
 348                 break;
 349
 350         default:
 351                 printf(", RAM %d(not supported)", feature_ramconfig);
 352                 break;
 353         }
 354
 355         printf(", %d carrier(s) %s", feature_carriers,
 356                feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
 357
 358         printf(", %d video channel(s)\n", feature_video_channels);
 359 }
 360
 361 int last_stage_init(void)
 362 {
 363         int slaves;
 364         unsigned int k;
 365         unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
 366         int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
 367         u16 fpga_features;
 368         int feature_carrier_speed = fpga_features & (1<<4);
 369
 370         FPGA_GET_REG(0, fpga_features, &fpga_features);
 371
 372         print_fpga_info(0);
 373         osd_probe(0);
 374
 375         /* wait for FPGA done */
 376         for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
 377                 unsigned int ctr = 0;
 378
 379                 if (i2c_probe(mclink_controllers[k]))
 380                         continue;
 381
 382                 while (!(pca953x_get_val(mclink_controllers[k])
 383                        & MCFPGA_DONE)) {
 384                         udelay(100000);
 385                         if (ctr++ > 5) {
 386                                 printf("no done for mclink_controller %d\n", k);
 387                                 break;
 388                         }
 389                 }
 390         }
 391
 392         if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
 393                 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
 394                                 bb_miiphy_write);
 395                 if (!verify_88e1518(bb_miiphy_buses[0].name, 0)) {
 396                         printf("Fixup 88e1518 erratum on %s\n",
 397                                bb_miiphy_buses[0].name);
 398                         setup_88e1518(bb_miiphy_buses[0].name, 0);
 399                 }
 400         }
 401
 402         /* wait for slave-PLLs to be up and running */
 403         udelay(500000);
 404
 405         mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
 406         slaves = mclink_probe();
 407         mclink_fpgacount = 0;
 408
 409         if (slaves <= 0)
 410                 return 0;
 411
 412         mclink_fpgacount = slaves;
 413
 414         for (k = 1; k <= slaves; ++k) {
 415                 FPGA_GET_REG(k, fpga_features, &fpga_features);
 416                 feature_carrier_speed = fpga_features & (1<<4);
 417
 418                 print_fpga_info(k);
 419                 osd_probe(k);
 420                 if (feature_carrier_speed == CARRIER_SPEED_1G) {
 421                         miiphy_register(bb_miiphy_buses[k].name,
 422                                         bb_miiphy_read, bb_miiphy_write);
 423                         if (!verify_88e1518(bb_miiphy_buses[k].name, 0)) {
 424                                 printf("Fixup 88e1518 erratum on %s\n",
 425                                        bb_miiphy_buses[k].name);
 426                                 setup_88e1518(bb_miiphy_buses[k].name, 0);
 427                         }
 428                 }
 429         }
 430
 431         return 0;
 432 }
 433
 434 /*
 435  * provide access to fpga gpios (for I2C bitbang)
 436  * (these may look all too simple but make iocon.h much more readable)
 437  */
 438 void fpga_gpio_set(unsigned int bus, int pin)
 439 {
 440         FPGA_SET_REG(bus, gpio.set, pin);
 441 }
 442
 443 void fpga_gpio_clear(unsigned int bus, int pin)
 444 {
 445         FPGA_SET_REG(bus, gpio.clear, pin);
 446 }
 447
 448 int fpga_gpio_get(unsigned int bus, int pin)
 449 {
 450         u16 val;
 451
 452         FPGA_GET_REG(bus, gpio.read, &val);
 453
 454         return val & pin;
 455 }
 456
 457 void gd405ep_init(void)
 458 {
 459         unsigned int k;
 460
 461         if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
 462                 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
 463                         gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
 464         } else {
 465                 pca9698_direction_output(0x20, 4, 1);
 466         }
 467 }
 468
 469 void gd405ep_set_fpga_reset(unsigned state)
 470 {
 471         int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
 472
 473         if (legacy) {
 474                 if (state) {
 475                         out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
 476                         out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
 477                 } else {
 478                         out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 479                         out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 480                 }
 481         } else {
 482                 pca9698_set_value(0x20, 4, state ? 0 : 1);
 483         }
 484 }
 485
 486 void gd405ep_setup_hw(void)
 487 {
 488         /*
 489          * set "startup-finished"-gpios
 490          */
 491         gpio_write_bit(21, 0);
 492         gpio_write_bit(22, 1);
 493 }
 494
 495 int gd405ep_get_fpga_done(unsigned fpga)
 496 {
 497         int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
 498
 499         if (legacy)
 500                 return in_le16((void *)LATCH2_BASE)
 501                        & CONFIG_SYS_FPGA_DONE(fpga);
 502         else
 503                 return pca9698_get_value(0x20, 20);
 504 }
 505
 506 /*
 507  * FPGA MII bitbang implementation
 508  */
 509
 510 struct fpga_mii {
 511         unsigned fpga;
 512         int mdio;
 513 } fpga_mii[] = {
 514         { 0, 1},
 515         { 1, 1},
 516         { 2, 1},
 517         { 3, 1},
 518 };
 519
 520 static int mii_dummy_init(struct bb_miiphy_bus *bus)
 521 {
 522         return 0;
 523 }
 524
 525 static int mii_mdio_active(struct bb_miiphy_bus *bus)
 526 {
 527         struct fpga_mii *fpga_mii = bus->priv;
 528
 529         if (fpga_mii->mdio)
 530                 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
 531         else
 532                 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
 533
 534         return 0;
 535 }
 536
 537 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
 538 {
 539         struct fpga_mii *fpga_mii = bus->priv;
 540
 541         FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
 542
 543         return 0;
 544 }
 545
 546 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
 547 {
 548         struct fpga_mii *fpga_mii = bus->priv;
 549
 550         if (v)
 551                 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
 552         else
 553                 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
 554
 555         fpga_mii->mdio = v;
 556
 557         return 0;
 558 }
 559
 560 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
 561 {
 562         u16 gpio;
 563         struct fpga_mii *fpga_mii = bus->priv;
 564
 565         FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
 566
 567         *v = ((gpio & GPIO_MDIO) != 0);
 568
 569         return 0;
 570 }
 571
 572 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
 573 {
 574         struct fpga_mii *fpga_mii = bus->priv;
 575
 576         if (v)
 577                 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
 578         else
 579                 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
 580
 581         return 0;
 582 }
 583
 584 static int mii_delay(struct bb_miiphy_bus *bus)
 585 {
 586         udelay(1);
 587
 588         return 0;
 589 }
 590
 591 struct bb_miiphy_bus bb_miiphy_buses[] = {
 592         {
 593                 .name = "trans1",
 594                 .init = mii_dummy_init,
 595                 .mdio_active = mii_mdio_active,
 596                 .mdio_tristate = mii_mdio_tristate,
 597                 .set_mdio = mii_set_mdio,
 598                 .get_mdio = mii_get_mdio,
 599                 .set_mdc = mii_set_mdc,
 600                 .delay = mii_delay,
 601                 .priv = &fpga_mii[0],
 602         },
 603         {
 604                 .name = "trans2",
 605                 .init = mii_dummy_init,
 606                 .mdio_active = mii_mdio_active,
 607                 .mdio_tristate = mii_mdio_tristate,
 608                 .set_mdio = mii_set_mdio,
 609                 .get_mdio = mii_get_mdio,
 610                 .set_mdc = mii_set_mdc,
 611                 .delay = mii_delay,
 612                 .priv = &fpga_mii[1],
 613         },
 614         {
 615                 .name = "trans3",
 616                 .init = mii_dummy_init,
 617                 .mdio_active = mii_mdio_active,
 618                 .mdio_tristate = mii_mdio_tristate,
 619                 .set_mdio = mii_set_mdio,
 620                 .get_mdio = mii_get_mdio,
 621                 .set_mdc = mii_set_mdc,
 622                 .delay = mii_delay,
 623                 .priv = &fpga_mii[2],
 624         },
 625         {
 626                 .name = "trans4",
 627                 .init = mii_dummy_init,
 628                 .mdio_active = mii_mdio_active,
 629                 .mdio_tristate = mii_mdio_tristate,
 630                 .set_mdio = mii_set_mdio,
 631                 .get_mdio = mii_get_mdio,
 632                 .set_mdc = mii_set_mdc,
 633                 .delay = mii_delay,
 634                 .priv = &fpga_mii[3],
 635         },
 636 };
 637
 638 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
 639                           sizeof(bb_miiphy_buses[0]);
 640
 641 /*
 642  * Workaround for erratum mentioned in 88E1518 release notes
 643  */
 644
 645 static int verify_88e1518(const char *bus, unsigned char addr)
 646 {
 647         u16 phy_id1, phy_id2;
 648
 649         if (miiphy_read(bus, addr, 2, &phy_id1) ||
 650             miiphy_read(bus, addr, 3, &phy_id2)) {
 651                 printf("Error reading from the PHY addr=%02x\n", addr);
 652                 return -EIO;
 653         }
 654
 655         if ((phy_id1 != 0x0141) || ((phy_id2 & 0xfff0) != 0x0dd0))
 656                 return -EINVAL;
 657
 658         return 0;
 659 }
 660
 661 struct regfix_88e1518 {
 662         u8 reg;
 663         u16 data;
 664 } regfix_88e1518[] = {
 665         { 22, 0x00ff },
 666         { 17, 0x214b },
 667         { 16, 0x2144 },
 668         { 17, 0x0c28 },
 669         { 16, 0x2146 },
 670         { 17, 0xb233 },
 671         { 16, 0x214d },
 672         { 17, 0xcc0c },
 673         { 16, 0x2159 },
 674         { 22, 0x00fb },
 675         {  7, 0xc00d },
 676         { 22, 0x0000 },
 677 };
 678
 679 static int setup_88e1518(const char *bus, unsigned char addr)
 680 {
 681         unsigned int k;
 682
 683         for (k = 0; k < ARRAY_SIZE(regfix_88e1518); ++k) {
 684                 if (miiphy_write(bus, addr,
 685                                  regfix_88e1518[k].reg,
 686                                  regfix_88e1518[k].data)) {
 687                         printf("Error writing to the PHY addr=%02x\n", addr);
 688                         return -1;
 689                 }
 690         }
 691
 692         return 0;
 693 }