board/gdsys/405ep/iocon.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <asm/ppc4xx-gpio.h>
  29
  30 #include "405ep.h"
  31 #include <gdsys_fpga.h>
  32
  33 #include "../common/osd.h"
  34
  35 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  36 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  37 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  38
  39 enum {
  40         UNITTYPE_MAIN_SERVER = 0,
  41         UNITTYPE_MAIN_USER = 1,
  42         UNITTYPE_VIDEO_SERVER = 2,
  43         UNITTYPE_VIDEO_USER = 3,
  44 };
  45
  46 enum {
  47         HWVER_100 = 0,
  48         HWVER_104 = 1,
  49         HWVER_110 = 2,
  50 };
  51
  52 enum {
  53         COMPRESSION_NONE = 0,
  54         COMPRESSION_TYPE1_DELTA,
  55 };
  56
  57 enum {
  58         AUDIO_NONE = 0,
  59         AUDIO_TX = 1,
  60         AUDIO_RX = 2,
  61         AUDIO_RXTX = 3,
  62 };
  63
  64 enum {
  65         SYSCLK_147456 = 0,
  66 };
  67
  68 enum {
  69         RAM_DDR2_32 = 0,
  70 };
  71
  72 /*
  73  * Check Board Identity:
  74  */
  75 int checkboard(void)
  76 {
  77         char buf[64];
  78         int i = getenv_f("serial#", buf, sizeof(buf));
  79         ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
  80         u16 versions = in_le16(&fpga->versions);
  81         u16 fpga_version = in_le16(&fpga->fpga_version);
  82         u16 fpga_features = in_le16(&fpga->fpga_features);
  83         unsigned unit_type;
  84         unsigned hardware_version;
  85         unsigned feature_compression;
  86         unsigned feature_osd;
  87         unsigned feature_audio;
  88         unsigned feature_sysclock;
  89         unsigned feature_ramconfig;
  90         unsigned feature_carriers;
  91         unsigned feature_video_channels;
  92
  93         unit_type = (versions & 0xf000) >> 12;
  94         hardware_version = versions & 0x000f;
  95         feature_compression = (fpga_features & 0xe000) >> 13;
  96         feature_osd = fpga_features & (1<<11);
  97         feature_audio = (fpga_features & 0x0600) >> 9;
  98         feature_sysclock = (fpga_features & 0x0180) >> 7;
  99         feature_ramconfig = (fpga_features & 0x0060) >> 5;
 100         feature_carriers = (fpga_features & 0x000c) >> 2;
 101         feature_video_channels = fpga_features & 0x0003;
 102
 103         printf("Board: ");
 104
 105         printf("IoCon");
 106
 107         if (i > 0) {
 108                 puts(", serial# ");
 109                 puts(buf);
 110         }
 111         puts("\n       ");
 112
 113         switch (unit_type) {
 114         case UNITTYPE_MAIN_USER:
 115                 printf("Mainchannel");
 116                 break;
 117
 118         case UNITTYPE_VIDEO_USER:
 119                 printf("Videochannel");
 120                 break;
 121
 122         default:
 123                 printf("UnitType %d(not supported)", unit_type);
 124                 break;
 125         }
 126
 127         switch (hardware_version) {
 128         case HWVER_100:
 129                 printf(" HW-Ver 1.00\n");
 130                 break;
 131
 132         case HWVER_104:
 133                 printf(" HW-Ver 1.04\n");
 134                 break;
 135
 136         case HWVER_110:
 137                 printf(" HW-Ver 1.10\n");
 138                 break;
 139
 140         default:
 141                 printf(" HW-Ver %d(not supported)\n",
 142                        hardware_version);
 143                 break;
 144         }
 145
 146         printf("       FPGA V %d.%02d, features:",
 147                 fpga_version / 100, fpga_version % 100);
 148
 149
 150         switch (feature_compression) {
 151         case COMPRESSION_NONE:
 152                 printf(" no compression");
 153                 break;
 154
 155         case COMPRESSION_TYPE1_DELTA:
 156                 printf(" type1-deltacompression");
 157                 break;
 158
 159         default:
 160                 printf(" compression %d(not supported)", feature_compression);
 161                 break;
 162         }
 163
 164         printf(", %sosd", feature_osd ? "" : "no ");
 165
 166         switch (feature_audio) {
 167         case AUDIO_NONE:
 168                 printf(", no audio");
 169                 break;
 170
 171         case AUDIO_TX:
 172                 printf(", audio tx");
 173                 break;
 174
 175         case AUDIO_RX:
 176                 printf(", audio rx");
 177                 break;
 178
 179         case AUDIO_RXTX:
 180                 printf(", audio rx+tx");
 181                 break;
 182
 183         default:
 184                 printf(", audio %d(not supported)", feature_audio);
 185                 break;
 186         }
 187
 188         puts(",\n       ");
 189
 190         switch (feature_sysclock) {
 191         case SYSCLK_147456:
 192                 printf("clock 147.456 MHz");
 193                 break;
 194
 195         default:
 196                 printf("clock %d(not supported)", feature_sysclock);
 197                 break;
 198         }
 199
 200         switch (feature_ramconfig) {
 201         case RAM_DDR2_32:
 202                 printf(", RAM 32 bit DDR2");
 203                 break;
 204
 205         default:
 206                 printf(", RAM %d(not supported)", feature_ramconfig);
 207                 break;
 208         }
 209
 210         printf(", %d carrier(s)", feature_carriers);
 211
 212         printf(", %d video channel(s)\n", feature_video_channels);
 213
 214         return 0;
 215 }
 216
 217 int last_stage_init(void)
 218 {
 219         return osd_probe(0);
 220 }
 221
 222 /*
 223  * provide access to fpga gpios (for I2C bitbang)
 224  */
 225 void fpga_gpio_set(int pin)
 226 {
 227         out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin);
 228 }
 229
 230 void fpga_gpio_clear(int pin)
 231 {
 232         out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin);
 233 }
 234
 235 int fpga_gpio_get(int pin)
 236 {
 237         return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
 238 }
 239
 240 void gd405ep_init(void)
 241 {
 242 }
 243
 244 void gd405ep_set_fpga_reset(unsigned state)
 245 {
 246         if (state) {
 247                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
 248                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
 249         } else {
 250                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 251                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 252         }
 253 }
 254
 255 void gd405ep_setup_hw(void)
 256 {
 257         /*
 258          * set "startup-finished"-gpios
 259          */
 260         gpio_write_bit(21, 0);
 261         gpio_write_bit(22, 1);
 262 }
 263
 264 int gd405ep_get_fpga_done(unsigned fpga)
 265 {
 266         return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
 267 }