3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/processor.h>
13 #include <asm/ppc4xx-gpio.h>
16 #include <gdsys_fpga.h>
18 #include "../common/dp501.h"
19 #include "../common/osd.h"
20 #include "../common/mclink.h"
28 DECLARE_GLOBAL_DATA_PTR;
30 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
31 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
32 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
34 #define MAX_MUX_CHANNELS 2
37 UNITTYPE_MAIN_SERVER = 0,
38 UNITTYPE_MAIN_USER = 1,
39 UNITTYPE_VIDEO_SERVER = 2,
40 UNITTYPE_VIDEO_USER = 3,
61 COMPRESSION_TYPE1_DELTA = 1,
62 COMPRESSION_TYPE1_TYPE2_DELTA = 3,
83 CARRIER_SPEED_2_5G = 1,
88 MCFPGA_INIT_N = 1 << 1,
89 MCFPGA_PROGRAM_N = 1 << 2,
90 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
91 MCFPGA_RESET_N = 1 << 4,
99 unsigned int mclink_fpgacount;
100 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
102 int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
104 static int setup_88e1518(const char *bus, unsigned char addr);
106 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
115 res = mclink_send(fpga - 1, regoff, data);
117 printf("mclink_send reg %02lx data %04x returned %d\n",
127 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
133 *data = in_le16(reg);
136 if (fpga > mclink_fpgacount)
138 res = mclink_receive(fpga - 1, regoff, data);
140 printf("mclink_receive reg %02lx returned %d\n",
150 * Check Board Identity:
154 char *s = getenv("serial#");
170 static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
176 unsigned hardware_version;
177 unsigned feature_compression;
178 unsigned feature_osd;
179 unsigned feature_audio;
180 unsigned feature_sysclock;
181 unsigned feature_ramconfig;
182 unsigned feature_carrier_speed;
183 unsigned feature_carriers;
184 unsigned feature_video_channels;
186 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
188 FPGA_GET_REG(0, versions, &versions);
189 FPGA_GET_REG(0, fpga_version, &fpga_version);
190 FPGA_GET_REG(0, fpga_features, &fpga_features);
192 unit_type = (versions & 0xf000) >> 12;
193 feature_compression = (fpga_features & 0xe000) >> 13;
194 feature_osd = fpga_features & (1<<11);
195 feature_audio = (fpga_features & 0x0600) >> 9;
196 feature_sysclock = (fpga_features & 0x0180) >> 7;
197 feature_ramconfig = (fpga_features & 0x0060) >> 5;
198 feature_carrier_speed = fpga_features & (1<<4);
199 feature_carriers = (fpga_features & 0x000c) >> 2;
200 feature_video_channels = fpga_features & 0x0003;
206 case UNITTYPE_MAIN_USER:
207 printf("Mainchannel");
210 case UNITTYPE_VIDEO_USER:
211 printf("Videochannel");
215 printf("UnitType %d(not supported)", unit_type);
219 if (unit_type == UNITTYPE_MAIN_USER) {
222 (in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
225 (!!pca9698_get_value(0x20, 24) << 0)
226 | (!!pca9698_get_value(0x20, 25) << 1)
227 | (!!pca9698_get_value(0x20, 26) << 2)
228 | (!!pca9698_get_value(0x20, 27) << 3);
229 switch (hardware_version) {
231 printf(" HW-Ver 1.00,");
235 printf(" HW-Ver 1.04,");
239 printf(" HW-Ver 1.10,");
243 printf(" HW-Ver 1.20-1.21,");
247 printf(" HW-Ver 2.00,");
251 printf(" HW-Ver 2.10,");
255 printf(" HW-Ver 2.20,");
259 printf(" HW-Ver 2.30,");
263 printf(" HW-Ver %d(not supported),",
271 if (unit_type == UNITTYPE_VIDEO_USER) {
272 hardware_version = versions & 0x000f;
273 switch (hardware_version) {
275 printf(" HW-Ver 2.00,");
279 printf(" HW-Ver 2.10,");
283 printf(" HW-Ver %d(not supported),",
289 printf(" FPGA V %d.%02d\n features:",
290 fpga_version / 100, fpga_version % 100);
293 switch (feature_compression) {
294 case COMPRESSION_NONE:
295 printf(" no compression");
298 case COMPRESSION_TYPE1_DELTA:
299 printf(" type1-deltacompression");
302 case COMPRESSION_TYPE1_TYPE2_DELTA:
303 printf(" type1-deltacompression, type2-inlinecompression");
307 printf(" compression %d(not supported)", feature_compression);
311 printf(", %sosd", feature_osd ? "" : "no ");
313 switch (feature_audio) {
315 printf(", no audio");
319 printf(", audio tx");
323 printf(", audio rx");
327 printf(", audio rx+tx");
331 printf(", audio %d(not supported)", feature_audio);
337 switch (feature_sysclock) {
339 printf("clock 147.456 MHz");
343 printf("clock %d(not supported)", feature_sysclock);
347 switch (feature_ramconfig) {
349 printf(", RAM 32 bit DDR2");
353 printf(", RAM 32 bit DDR3");
357 printf(", RAM %d(not supported)", feature_ramconfig);
361 printf(", %d carrier(s) %s", feature_carriers,
362 feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
364 printf(", %d video channel(s)\n", feature_video_channels);
367 int last_stage_init(void)
372 unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
373 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
375 int feature_carrier_speed = fpga_features & (1<<4);
376 bool ch0_rgmii2_present = false;
377 int old_bus = i2c_get_bus_num();
379 FPGA_GET_REG(0, fpga_features, &fpga_features);
381 /* Turn on Parade DP501 */
382 pca9698_direction_output(0x20, 9, 1);
385 i2c_set_bus_num(dp501_i2c[0]);
387 i2c_set_bus_num(old_bus);
390 ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
392 print_fpga_info(0, ch0_rgmii2_present);
395 /* wait for FPGA done */
396 for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
397 unsigned int ctr = 0;
399 if (i2c_probe(mclink_controllers[k]))
402 while (!(pca953x_get_val(mclink_controllers[k])
406 printf("no done for mclink_controller %d\n", k);
412 if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
413 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
415 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
416 if ((mux_ch == 1) && !ch0_rgmii2_present)
419 setup_88e1518(bb_miiphy_buses[0].name, mux_ch);
423 /* wait for slave-PLLs to be up and running */
426 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
427 slaves = mclink_probe();
428 mclink_fpgacount = 0;
433 mclink_fpgacount = slaves;
435 for (k = 1; k <= slaves; ++k) {
436 FPGA_GET_REG(k, fpga_features, &fpga_features);
437 feature_carrier_speed = fpga_features & (1<<4);
439 print_fpga_info(k, false);
441 if (feature_carrier_speed == CARRIER_SPEED_1G) {
442 miiphy_register(bb_miiphy_buses[k].name,
443 bb_miiphy_read, bb_miiphy_write);
444 setup_88e1518(bb_miiphy_buses[k].name, 0);
452 * provide access to fpga gpios (for I2C bitbang)
453 * (these may look all too simple but make iocon.h much more readable)
455 void fpga_gpio_set(unsigned int bus, int pin)
457 FPGA_SET_REG(bus, gpio.set, pin);
460 void fpga_gpio_clear(unsigned int bus, int pin)
462 FPGA_SET_REG(bus, gpio.clear, pin);
465 int fpga_gpio_get(unsigned int bus, int pin)
469 FPGA_GET_REG(bus, gpio.read, &val);
474 void gd405ep_init(void)
478 if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
479 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
480 gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
482 pca9698_direction_output(0x20, 4, 1);
486 void gd405ep_set_fpga_reset(unsigned state)
488 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
492 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
493 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
495 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
496 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
499 pca9698_set_value(0x20, 4, state ? 0 : 1);
503 void gd405ep_setup_hw(void)
506 * set "startup-finished"-gpios
508 gpio_write_bit(21, 0);
509 gpio_write_bit(22, 1);
512 int gd405ep_get_fpga_done(unsigned fpga)
514 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
517 return in_le16((void *)LATCH2_BASE)
518 & CONFIG_SYS_FPGA_DONE(fpga);
520 return pca9698_get_value(0x20, 20);
524 * FPGA MII bitbang implementation
537 static int mii_dummy_init(struct bb_miiphy_bus *bus)
542 static int mii_mdio_active(struct bb_miiphy_bus *bus)
544 struct fpga_mii *fpga_mii = bus->priv;
547 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
549 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
554 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
556 struct fpga_mii *fpga_mii = bus->priv;
558 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
563 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
565 struct fpga_mii *fpga_mii = bus->priv;
568 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
570 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
577 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
580 struct fpga_mii *fpga_mii = bus->priv;
582 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
584 *v = ((gpio & GPIO_MDIO) != 0);
589 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
591 struct fpga_mii *fpga_mii = bus->priv;
594 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
596 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
601 static int mii_delay(struct bb_miiphy_bus *bus)
608 struct bb_miiphy_bus bb_miiphy_buses[] = {
611 .init = mii_dummy_init,
612 .mdio_active = mii_mdio_active,
613 .mdio_tristate = mii_mdio_tristate,
614 .set_mdio = mii_set_mdio,
615 .get_mdio = mii_get_mdio,
616 .set_mdc = mii_set_mdc,
618 .priv = &fpga_mii[0],
622 .init = mii_dummy_init,
623 .mdio_active = mii_mdio_active,
624 .mdio_tristate = mii_mdio_tristate,
625 .set_mdio = mii_set_mdio,
626 .get_mdio = mii_get_mdio,
627 .set_mdc = mii_set_mdc,
629 .priv = &fpga_mii[1],
633 .init = mii_dummy_init,
634 .mdio_active = mii_mdio_active,
635 .mdio_tristate = mii_mdio_tristate,
636 .set_mdio = mii_set_mdio,
637 .get_mdio = mii_get_mdio,
638 .set_mdc = mii_set_mdc,
640 .priv = &fpga_mii[2],
644 .init = mii_dummy_init,
645 .mdio_active = mii_mdio_active,
646 .mdio_tristate = mii_mdio_tristate,
647 .set_mdio = mii_set_mdio,
648 .get_mdio = mii_get_mdio,
649 .set_mdc = mii_set_mdc,
651 .priv = &fpga_mii[3],
655 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
656 sizeof(bb_miiphy_buses[0]);
662 MIICMD_WAIT_FOR_VALUE,
665 struct mii_setupcmd {
674 * verify we are talking to a 88e1518
676 struct mii_setupcmd verify_88e1518[] = {
677 { MIICMD_SET, 22, 0x0000 },
678 { MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff },
679 { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 },
683 * workaround for erratum mentioned in 88E1518 release notes
685 struct mii_setupcmd fixup_88e1518[] = {
686 { MIICMD_SET, 22, 0x00ff },
687 { MIICMD_SET, 17, 0x214b },
688 { MIICMD_SET, 16, 0x2144 },
689 { MIICMD_SET, 17, 0x0c28 },
690 { MIICMD_SET, 16, 0x2146 },
691 { MIICMD_SET, 17, 0xb233 },
692 { MIICMD_SET, 16, 0x214d },
693 { MIICMD_SET, 17, 0xcc0c },
694 { MIICMD_SET, 16, 0x2159 },
695 { MIICMD_SET, 22, 0x00fb },
696 { MIICMD_SET, 7, 0xc00d },
697 { MIICMD_SET, 22, 0x0000 },
701 * default initialization:
702 * - set RGMII receive timing to "receive clock transition when data stable"
703 * - set RGMII transmit timing to "transmit clock internally delayed"
704 * - set RGMII output impedance target to 78,8 Ohm
705 * - run output impedance calibration
706 * - set autonegotiation advertise to 1000FD only
708 struct mii_setupcmd default_88e1518[] = {
709 { MIICMD_SET, 22, 0x0002 },
710 { MIICMD_MODIFY, 21, 0x0030, 0x0030 },
711 { MIICMD_MODIFY, 25, 0x0000, 0x0003 },
712 { MIICMD_MODIFY, 24, 0x8000, 0x8000 },
713 { MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 },
714 { MIICMD_SET, 22, 0x0000 },
715 { MIICMD_MODIFY, 4, 0x0000, 0x01e0 },
716 { MIICMD_MODIFY, 9, 0x0200, 0x0300 },
720 * turn off CLK125 for PHY daughterboard
722 struct mii_setupcmd ch1fix_88e1518[] = {
723 { MIICMD_SET, 22, 0x0002 },
724 { MIICMD_MODIFY, 16, 0x0006, 0x0006 },
725 { MIICMD_SET, 22, 0x0000 },
729 * perform copper software reset
731 struct mii_setupcmd swreset_88e1518[] = {
732 { MIICMD_SET, 22, 0x0000 },
733 { MIICMD_MODIFY, 0, 0x8000, 0x8000 },
734 { MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 },
737 static int process_setupcmd(const char *bus, unsigned char addr,
738 struct mii_setupcmd *setupcmd)
741 u8 reg = setupcmd->reg;
742 u16 data = setupcmd->data;
743 u16 mask = setupcmd->mask;
744 u32 timeout = setupcmd->timeout;
748 debug("mii %s:%u reg %2u ", bus, addr, reg);
750 switch (setupcmd->token) {
752 res = miiphy_read(bus, addr, reg, &orig_data);
755 debug("is %04x. (value %04x mask %04x) ", orig_data, data,
757 data = (orig_data & ~mask) | (data & mask);
759 debug("=> %04x\n", data);
760 res = miiphy_write(bus, addr, reg, data);
762 case MIICMD_VERIFY_VALUE:
763 res = miiphy_read(bus, addr, reg, &orig_data);
766 if ((orig_data & mask) != (data & mask))
768 debug("(value %04x mask %04x) == %04x? %s\n", data, mask,
769 orig_data, res ? "FAIL" : "PASS");
771 case MIICMD_WAIT_FOR_VALUE:
773 start = get_timer(0);
774 while ((res != 0) && (get_timer(start) < timeout)) {
775 res = miiphy_read(bus, addr, reg, &orig_data);
778 if ((orig_data & mask) != (data & mask))
781 debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data,
782 mask, orig_data, res ? "FAIL" : "PASS",
793 static int process_setup(const char *bus, unsigned char addr,
794 struct mii_setupcmd *setupcmd, unsigned int count)
799 for (k = 0; k < count; ++k) {
800 res = process_setupcmd(bus, addr, &setupcmd[k]);
802 printf("mii cmd %u on bus %s addr %u failed, aborting setup",
803 setupcmd[k].token, bus, addr);
811 static int setup_88e1518(const char *bus, unsigned char addr)
815 res = process_setup(bus, addr,
816 verify_88e1518, ARRAY_SIZE(verify_88e1518));
820 res = process_setup(bus, addr,
821 fixup_88e1518, ARRAY_SIZE(fixup_88e1518));
825 res = process_setup(bus, addr,
826 default_88e1518, ARRAY_SIZE(default_88e1518));
831 res = process_setup(bus, addr,
832 ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518));
837 res = process_setup(bus, addr,
838 swreset_88e1518, ARRAY_SIZE(swreset_88e1518));