3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/ppc4xx-gpio.h>
34 #include <gdsys_fpga.h>
36 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
37 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
38 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
40 #define PHYREG_CONTROL 0
41 #define PHYREG_PAGE_ADDRESS 22
42 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
43 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
46 UNITTYPE_CCD_SWITCH = 1,
64 int configure_gbit_phy(unsigned char addr)
69 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
70 PHYREG_PAGE_ADDRESS, 0x0002))
72 /* disable SGMII autonegotiation */
73 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
74 PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
77 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
78 PHYREG_PAGE_ADDRESS, 0x0000))
80 /* switch from powerdown to normal operation */
81 if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
82 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
84 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
85 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
87 /* reset phy so settings take effect */
88 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
89 PHYREG_CONTROL, 0x9140))
95 printf("Error writing to the PHY addr=%02x\n", addr);
100 * Check Board Identity:
104 char *s = getenv("serial#");
106 puts("Board: CATCenter Io");
118 static void print_fpga_info(void)
120 struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
121 u16 versions = in_le16(&fpga->versions);
122 u16 fpga_version = in_le16(&fpga->fpga_version);
123 u16 fpga_features = in_le16(&fpga->fpga_features);
125 unsigned hardware_version;
126 unsigned feature_channels;
127 unsigned feature_expansion;
129 unit_type = (versions & 0xf000) >> 12;
130 hardware_version = versions & 0x000f;
131 feature_channels = fpga_features & 0x007f;
132 feature_expansion = fpga_features & (1<<15);
137 case UNITTYPE_CCD_SWITCH:
138 printf("CCD-Switch");
142 printf("UnitType %d(not supported)", unit_type);
146 switch (hardware_version) {
148 printf(" HW-Ver 1.00\n");
152 printf(" HW-Ver 1.10\n");
156 printf(" HW-Ver 1.21\n");
160 printf(" HW-Ver 1.22\n");
164 printf(" HW-Ver %d(not supported)\n",
169 printf(" FPGA V %d.%02d, features:",
170 fpga_version / 100, fpga_version % 100);
172 printf(" %d channel(s)", feature_channels);
174 printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
180 int last_stage_init(void)
182 struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
187 miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
188 bb_miiphy_read, bb_miiphy_write);
190 for (k = 0; k < 32; ++k)
191 configure_gbit_phy(k);
193 /* take fpga serdes blocks out of reset */
194 out_le16(&fpga->quad_serdes_reset, 0);
199 void gd405ep_init(void)
203 void gd405ep_set_fpga_reset(unsigned state)
206 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
207 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
209 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
210 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
214 void gd405ep_setup_hw(void)
217 * set "startup-finished"-gpios
219 gpio_write_bit(21, 0);
220 gpio_write_bit(22, 1);
223 int gd405ep_get_fpga_done(unsigned fpga)
225 return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);