board/gdsys/405ep/dlvision-10g.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <asm/ppc4xx-gpio.h>
  29 #include <dtt.h>
  30
  31 #include "405ep.h"
  32 #include <gdsys_fpga.h>
  33
  34 #include "../common/osd.h"
  35
  36 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  37 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  38 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  39 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
  40
  41 #define LATCH2_MC2_PRESENT_N 0x0080
  42
  43 enum {
  44         UNITTYPE_VIDEO_USER = 0,
  45         UNITTYPE_MAIN_USER = 1,
  46         UNITTYPE_VIDEO_SERVER = 2,
  47         UNITTYPE_MAIN_SERVER = 3,
  48 };
  49
  50 enum {
  51         HWVER_101 = 0,
  52         HWVER_110 = 1,
  53 };
  54
  55 enum {
  56         AUDIO_NONE = 0,
  57         AUDIO_TX = 1,
  58         AUDIO_RX = 2,
  59         AUDIO_RXTX = 3,
  60 };
  61
  62 enum {
  63         SYSCLK_156250 = 2,
  64 };
  65
  66 enum {
  67         RAM_NONE = 0,
  68         RAM_DDR2_32 = 1,
  69         RAM_DDR2_64 = 2,
  70 };
  71
  72 int misc_init_r(void)
  73 {
  74         /* startup fans */
  75         dtt_init();
  76
  77         return 0;
  78 }
  79
  80 static unsigned int get_hwver(void)
  81 {
  82         u16 latch3 = in_le16((void *)LATCH3_BASE);
  83
  84         return latch3 & 0x0003;
  85 }
  86
  87 static unsigned int get_mc2_present(void)
  88 {
  89         u16 latch2 = in_le16((void *)LATCH2_BASE);
  90
  91         return !(latch2 & LATCH2_MC2_PRESENT_N);
  92 }
  93
  94 static void print_fpga_info(unsigned dev)
  95 {
  96         ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
  97         u16 versions = in_le16(&fpga->versions);
  98         u16 fpga_version = in_le16(&fpga->fpga_version);
  99         u16 fpga_features = in_le16(&fpga->fpga_features);
 100         unsigned unit_type;
 101         unsigned hardware_version;
 102         unsigned feature_rs232;
 103         unsigned feature_audio;
 104         unsigned feature_sysclock;
 105         unsigned feature_ramconfig;
 106         unsigned feature_carrier_speed;
 107         unsigned feature_carriers;
 108         unsigned feature_video_channels;
 109         int fpga_state = get_fpga_state(dev);
 110
 111         printf("FPGA%d: ", dev);
 112
 113         hardware_version = versions & 0x000f;
 114
 115         if (fpga_state
 116             && !((hardware_version == HWVER_101)
 117                  && (fpga_state == FPGA_STATE_DONE_FAILED))) {
 118                 puts("not available\n");
 119                 print_fpga_state(dev);
 120                 return;
 121         }
 122
 123         unit_type = (versions >> 4) & 0x000f;
 124         hardware_version = versions & 0x000f;
 125         feature_rs232 = fpga_features & (1<<11);
 126         feature_audio = (fpga_features >> 9) & 0x0003;
 127         feature_sysclock = (fpga_features >> 7) & 0x0003;
 128         feature_ramconfig = (fpga_features >> 5) & 0x0003;
 129         feature_carrier_speed = fpga_features & (1<<4);
 130         feature_carriers = (fpga_features >> 2) & 0x0003;
 131         feature_video_channels = fpga_features & 0x0003;
 132
 133         switch (unit_type) {
 134         case UNITTYPE_VIDEO_USER:
 135                 printf("Videochannel Userside");
 136                 break;
 137
 138         case UNITTYPE_MAIN_USER:
 139                 printf("Mainchannel Userside");
 140                 break;
 141
 142         case UNITTYPE_VIDEO_SERVER:
 143                 printf("Videochannel Serverside");
 144                 break;
 145
 146         case UNITTYPE_MAIN_SERVER:
 147                 printf("Mainchannel Serverside");
 148                 break;
 149
 150         default:
 151                 printf("UnitType %d(not supported)", unit_type);
 152                 break;
 153         }
 154
 155         switch (hardware_version) {
 156         case HWVER_101:
 157                 printf(" HW-Ver 1.01\n");
 158                 break;
 159
 160         case HWVER_110:
 161                 printf(" HW-Ver 1.10\n");
 162                 break;
 163
 164         default:
 165                 printf(" HW-Ver %d(not supported)\n",
 166                        hardware_version);
 167                 break;
 168         }
 169
 170         printf("       FPGA V %d.%02d, features:",
 171                 fpga_version / 100, fpga_version % 100);
 172
 173         printf(" %sRS232", feature_rs232 ? "" : "no ");
 174
 175         switch (feature_audio) {
 176         case AUDIO_NONE:
 177                 printf(", no audio");
 178                 break;
 179
 180         case AUDIO_TX:
 181                 printf(", audio tx");
 182                 break;
 183
 184         case AUDIO_RX:
 185                 printf(", audio rx");
 186                 break;
 187
 188         case AUDIO_RXTX:
 189                 printf(", audio rx+tx");
 190                 break;
 191
 192         default:
 193                 printf(", audio %d(not supported)", feature_audio);
 194                 break;
 195         }
 196
 197         switch (feature_sysclock) {
 198         case SYSCLK_156250:
 199                 printf(", clock 156.25 MHz");
 200                 break;
 201
 202         default:
 203                 printf(", clock %d(not supported)", feature_sysclock);
 204                 break;
 205         }
 206
 207         puts(",\n       ");
 208
 209         switch (feature_ramconfig) {
 210         case RAM_NONE:
 211                 printf("no RAM");
 212                 break;
 213
 214         case RAM_DDR2_32:
 215                 printf("RAM 32 bit DDR2");
 216                 break;
 217
 218         case RAM_DDR2_64:
 219                 printf("RAM 64 bit DDR2");
 220                 break;
 221
 222         default:
 223                 printf("RAM %d(not supported)", feature_ramconfig);
 224                 break;
 225         }
 226
 227         printf(", %d carrier(s) %s", feature_carriers,
 228                 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
 229
 230         printf(", %d video channel(s)\n", feature_video_channels);
 231 }
 232
 233 /*
 234  * Check Board Identity:
 235  */
 236 int checkboard(void)
 237 {
 238         char *s = getenv("serial#");
 239
 240         puts("Board: ");
 241
 242         puts("DLVision 10G");
 243
 244         if (s != NULL) {
 245                 puts(", serial# ");
 246                 puts(s);
 247         }
 248
 249         puts("\n");
 250
 251         return 0;
 252 }
 253
 254 int last_stage_init(void)
 255 {
 256         ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 257         u16 versions = in_le16(&fpga->versions);
 258
 259         print_fpga_info(0);
 260         if (get_mc2_present())
 261                 print_fpga_info(1);
 262
 263         if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
 264                 return 0;
 265
 266         if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
 267                 osd_probe(0);
 268
 269         if (get_mc2_present() &&
 270             (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
 271                 osd_probe(1);
 272
 273         return 0;
 274 }
 275
 276 void gd405ep_init(void)
 277 {
 278 }
 279
 280 void gd405ep_set_fpga_reset(unsigned state)
 281 {
 282         if (state) {
 283                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
 284                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
 285         } else {
 286                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 287                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 288         }
 289 }
 290
 291 void gd405ep_setup_hw(void)
 292 {
 293         /*
 294          * set "startup-finished"-gpios
 295          */
 296         gpio_write_bit(21, 0);
 297         gpio_write_bit(22, 1);
 298 }
 299
 300 int gd405ep_get_fpga_done(unsigned fpga)
 301 {
 302         return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
 303 }