board/gdsys/405ep/dlvision-10g.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <asm/ppc4xx-gpio.h>
  29
  30 #include "405ep.h"
  31 #include <gdsys_fpga.h>
  32
  33 #include "../common/osd.h"
  34
  35 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  36 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  37 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  38 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
  39
  40 #define LATCH2_MC2_PRESENT_N 0x0080
  41
  42 enum {
  43         UNITTYPE_VIDEO_USER = 0,
  44         UNITTYPE_MAIN_USER = 1,
  45         UNITTYPE_VIDEO_SERVER = 2,
  46         UNITTYPE_MAIN_SERVER = 3,
  47 };
  48
  49 enum {
  50         HWVER_101 = 0,
  51         HWVER_110 = 1,
  52 };
  53
  54 enum {
  55         AUDIO_NONE = 0,
  56         AUDIO_TX = 1,
  57         AUDIO_RX = 2,
  58         AUDIO_RXTX = 3,
  59 };
  60
  61 enum {
  62         SYSCLK_156250 = 2,
  63 };
  64
  65 enum {
  66         RAM_NONE = 0,
  67         RAM_DDR2_32 = 1,
  68         RAM_DDR2_64 = 2,
  69 };
  70
  71 static unsigned int get_hwver(void)
  72 {
  73         u16 latch3 = in_le16((void *)LATCH3_BASE);
  74
  75         return latch3 & 0x0003;
  76 }
  77
  78 static unsigned int get_mc2_present(void)
  79 {
  80         u16 latch2 = in_le16((void *)LATCH2_BASE);
  81
  82         return !(latch2 & LATCH2_MC2_PRESENT_N);
  83 }
  84
  85 static void print_fpga_info(unsigned dev)
  86 {
  87         ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
  88         u16 versions = in_le16(&fpga->versions);
  89         u16 fpga_version = in_le16(&fpga->fpga_version);
  90         u16 fpga_features = in_le16(&fpga->fpga_features);
  91         unsigned unit_type;
  92         unsigned hardware_version;
  93         unsigned feature_rs232;
  94         unsigned feature_audio;
  95         unsigned feature_sysclock;
  96         unsigned feature_ramconfig;
  97         unsigned feature_carrier_speed;
  98         unsigned feature_carriers;
  99         unsigned feature_video_channels;
 100         int fpga_state = get_fpga_state(dev);
 101
 102         printf("FPGA%d: ", dev);
 103
 104         hardware_version = versions & 0x000f;
 105
 106         if (fpga_state
 107             && !((hardware_version == HWVER_101)
 108                  && (fpga_state == FPGA_STATE_DONE_FAILED))) {
 109                 puts("not available\n");
 110                 print_fpga_state(dev);
 111                 return;
 112         }
 113
 114         unit_type = (versions >> 4) & 0x000f;
 115         hardware_version = versions & 0x000f;
 116         feature_rs232 = fpga_features & (1<<11);
 117         feature_audio = (fpga_features >> 9) & 0x0003;
 118         feature_sysclock = (fpga_features >> 7) & 0x0003;
 119         feature_ramconfig = (fpga_features >> 5) & 0x0003;
 120         feature_carrier_speed = fpga_features & (1<<4);
 121         feature_carriers = (fpga_features >> 2) & 0x0003;
 122         feature_video_channels = fpga_features & 0x0003;
 123
 124         switch (unit_type) {
 125         case UNITTYPE_VIDEO_USER:
 126                 printf("Videochannel Userside");
 127                 break;
 128
 129         case UNITTYPE_MAIN_USER:
 130                 printf("Mainchannel Userside");
 131                 break;
 132
 133         case UNITTYPE_VIDEO_SERVER:
 134                 printf("Videochannel Serverside");
 135                 break;
 136
 137         case UNITTYPE_MAIN_SERVER:
 138                 printf("Mainchannel Serverside");
 139                 break;
 140
 141         default:
 142                 printf("UnitType %d(not supported)", unit_type);
 143                 break;
 144         }
 145
 146         switch (hardware_version) {
 147         case HWVER_101:
 148                 printf(" HW-Ver 1.01\n");
 149                 break;
 150
 151         case HWVER_110:
 152                 printf(" HW-Ver 1.10\n");
 153                 break;
 154
 155         default:
 156                 printf(" HW-Ver %d(not supported)\n",
 157                        hardware_version);
 158                 break;
 159         }
 160
 161         printf("       FPGA V %d.%02d, features:",
 162                 fpga_version / 100, fpga_version % 100);
 163
 164         printf(" %sRS232", feature_rs232 ? "" : "no ");
 165
 166         switch (feature_audio) {
 167         case AUDIO_NONE:
 168                 printf(", no audio");
 169                 break;
 170
 171         case AUDIO_TX:
 172                 printf(", audio tx");
 173                 break;
 174
 175         case AUDIO_RX:
 176                 printf(", audio rx");
 177                 break;
 178
 179         case AUDIO_RXTX:
 180                 printf(", audio rx+tx");
 181                 break;
 182
 183         default:
 184                 printf(", audio %d(not supported)", feature_audio);
 185                 break;
 186         }
 187
 188         switch (feature_sysclock) {
 189         case SYSCLK_156250:
 190                 printf(", clock 156.25 MHz");
 191                 break;
 192
 193         default:
 194                 printf(", clock %d(not supported)", feature_sysclock);
 195                 break;
 196         }
 197
 198         puts(",\n       ");
 199
 200         switch (feature_ramconfig) {
 201         case RAM_NONE:
 202                 printf("no RAM");
 203                 break;
 204
 205         case RAM_DDR2_32:
 206                 printf("RAM 32 bit DDR2");
 207                 break;
 208
 209         case RAM_DDR2_64:
 210                 printf("RAM 64 bit DDR2");
 211                 break;
 212
 213         default:
 214                 printf("RAM %d(not supported)", feature_ramconfig);
 215                 break;
 216         }
 217
 218         printf(", %d carrier(s) %s", feature_carriers,
 219                 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
 220
 221         printf(", %d video channel(s)\n", feature_video_channels);
 222 }
 223
 224 /*
 225  * Check Board Identity:
 226  */
 227 int checkboard(void)
 228 {
 229         char buf[64];
 230         int i = getenv_f("serial#", buf, sizeof(buf));
 231
 232         printf("Board: ");
 233
 234         printf("DLVision 10G");
 235
 236         if (i > 0) {
 237                 puts(", serial# ");
 238                 puts(buf);
 239         }
 240
 241         puts("\n");
 242
 243         print_fpga_info(0);
 244         if (get_mc2_present())
 245                 print_fpga_info(1);
 246
 247         return 0;
 248 }
 249
 250 int last_stage_init(void)
 251 {
 252         ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 253         u16 versions = in_le16(&fpga->versions);
 254
 255         if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
 256                 return 0;
 257
 258         if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
 259                 osd_probe(0);
 260
 261         if (get_mc2_present() &&
 262             (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
 263                 osd_probe(1);
 264
 265         return 0;
 266 }
 267
 268 void gd405ep_init(void)
 269 {
 270 }
 271
 272 void gd405ep_set_fpga_reset(unsigned state)
 273 {
 274         if (state) {
 275                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
 276                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
 277         } else {
 278                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 279                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 280         }
 281 }
 282
 283 void gd405ep_setup_hw(void)
 284 {
 285         /*
 286          * set "startup-finished"-gpios
 287          */
 288         gpio_write_bit(21, 0);
 289         gpio_write_bit(22, 1);
 290 }
 291
 292 int gd405ep_get_fpga_done(unsigned fpga)
 293 {
 294         return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
 295 }