board/gdsys/405ep/405ep.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <asm/ppc4xx-gpio.h>
  29 #include <asm/global_data.h>
  30
  31 #include <gdsys_fpga.h>
  32
  33 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  34 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  35 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  36
  37 #define REFLECTION_TESTPATTERN 0xdede
  38 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 int get_fpga_state(unsigned dev)
  43 {
  44         return gd->fpga_state[dev];
  45 }
  46
  47 void print_fpga_state(unsigned dev)
  48 {
  49         if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
  50                 puts("       Waiting for FPGA-DONE timed out.\n");
  51         if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
  52                 puts("       FPGA reflection test failed.\n");
  53 }
  54
  55 int board_early_init_f(void)
  56 {
  57         unsigned k;
  58         unsigned ctr;
  59
  60         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  61                 gd->fpga_state[k] = 0;
  62
  63         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  64         mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
  65         mtdcr(UIC0CR, 0x00000000);      /* set all to be non-critical */
  66         mtdcr(UIC0PR, 0xFFFFFF80);      /* set int polarities */
  67         mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
  68         mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest prio */
  69         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  70
  71         /*
  72          * EBC Configuration Register: set ready timeout to 512 ebc-clks
  73          * -> ca. 15 us
  74          */
  75         mtebc(EBC0_CFG, 0xa8400000);    /* ebc always driven */
  76
  77         /*
  78          * setup io-latches for reset
  79          */
  80         out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
  81         out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
  82
  83         /*
  84          * set "startup-finished"-gpios
  85          */
  86         gpio_write_bit(21, 0);
  87         gpio_write_bit(22, 1);
  88
  89         /*
  90          * wait for fpga-done
  91          */
  92         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  93                 ctr = 0;
  94                 while (!(in_le16((void *)LATCH2_BASE)
  95                         & CONFIG_SYS_FPGA_DONE(k))) {
  96                         udelay(100000);
  97                         if (ctr++ > 5) {
  98                                 gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
  99                                 break;
 100                         }
 101                 }
 102         }
 103
 104         /*
 105          * setup io-latches for boot (stop reset)
 106          */
 107         udelay(10);
 108         out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 109         out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 110
 111         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
 112                 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
 113                 /*
 114                  * wait for fpga out of reset
 115                  */
 116                 ctr = 0;
 117                 while (1) {
 118                         out_le16(&fpga->reflection_low,
 119                                 REFLECTION_TESTPATTERN);
 120                         if (in_le16(&fpga->reflection_high) ==
 121                                 REFLECTION_TESTPATTERN_INV)
 122                                 break;
 123                         udelay(100000);
 124                         if (ctr++ > 5) {
 125                                 gd->fpga_state[k] |=
 126                                         FPGA_STATE_REFLECTION_FAILED;
 127                                 break;
 128                         }
 129                 }
 130         }
 131
 132         return 0;
 133 }