3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/ppc4xx-gpio.h>
13 #include <asm/global_data.h>
16 #include <gdsys_fpga.h>
18 #define REFLECTION_TESTPATTERN 0xdede
19 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
21 DECLARE_GLOBAL_DATA_PTR;
23 int get_fpga_state(unsigned dev)
25 return gd->arch.fpga_state[dev];
28 void print_fpga_state(unsigned dev)
30 if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
31 puts(" Waiting for FPGA-DONE timed out.\n");
32 if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
33 puts(" FPGA reflection test failed.\n");
36 int board_early_init_f(void)
40 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
41 gd->arch.fpga_state[k] = 0;
43 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
44 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
45 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
46 mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
47 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
48 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
49 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
52 * EBC Configuration Register: set ready timeout to 512 ebc-clks
55 mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
59 int board_early_init_r(void)
64 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
65 gd->arch.fpga_state[k] = 0;
72 gd405ep_set_fpga_reset(1);
76 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
78 while (!gd405ep_get_fpga_done(k)) {
81 gd->arch.fpga_state[k] |=
82 FPGA_STATE_DONE_FAILED;
90 gd405ep_set_fpga_reset(0);
92 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
93 struct ihs_fpga *fpga =
94 (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
95 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
96 u16 *reflection_target = &fpga->reflection_low;
98 u16 *reflection_target = &fpga->reflection_high;
101 * wait for fpga out of reset
105 out_le16(&fpga->reflection_low,
106 REFLECTION_TESTPATTERN);
108 if (in_le16(reflection_target) ==
109 REFLECTION_TESTPATTERN_INV)
114 gd->arch.fpga_state[k] |=
115 FPGA_STATE_REFLECTION_FAILED;