board/gdsys/405ep/405ep.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <asm/processor.h>
  11 #include <asm/io.h>
  12 #include <asm/ppc4xx-gpio.h>
  13 #include <asm/global_data.h>
  14
  15 #include "405ep.h"
  16 #include <gdsys_fpga.h>
  17
  18 #define REFLECTION_TESTPATTERN 0xdede
  19 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 int get_fpga_state(unsigned dev)
  24 {
  25         return gd->arch.fpga_state[dev];
  26 }
  27
  28 void print_fpga_state(unsigned dev)
  29 {
  30         if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
  31                 puts("       Waiting for FPGA-DONE timed out.\n");
  32         if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
  33                 puts("       FPGA reflection test failed.\n");
  34 }
  35
  36 int board_early_init_f(void)
  37 {
  38         unsigned k;
  39
  40         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  41                 gd->arch.fpga_state[k] = 0;
  42
  43         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  44         mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
  45         mtdcr(UIC0CR, 0x00000000);      /* set all to be non-critical */
  46         mtdcr(UIC0PR, 0xFFFFFF80);      /* set int polarities */
  47         mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
  48         mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest prio */
  49         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  50
  51         /*
  52          * EBC Configuration Register: set ready timeout to 512 ebc-clks
  53          * -> ca. 15 us
  54          */
  55         mtebc(EBC0_CFG, 0xa8400000);    /* ebc always driven */
  56         return 0;
  57 }
  58
  59 int board_early_init_r(void)
  60 {
  61         unsigned k;
  62         unsigned ctr;
  63
  64         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  65                 gd->arch.fpga_state[k] = 0;
  66
  67         /*
  68          * reset FPGA
  69          */
  70         gd405ep_init();
  71
  72         gd405ep_set_fpga_reset(1);
  73
  74         gd405ep_setup_hw();
  75
  76         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  77                 ctr = 0;
  78                 while (!gd405ep_get_fpga_done(k)) {
  79                         udelay(100000);
  80                         if (ctr++ > 5) {
  81                                 gd->arch.fpga_state[k] |=
  82                                         FPGA_STATE_DONE_FAILED;
  83                                 break;
  84                         }
  85                 }
  86         }
  87
  88         udelay(10);
  89
  90         gd405ep_set_fpga_reset(0);
  91
  92         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  93                 struct ihs_fpga *fpga =
  94                         (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
  95 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
  96                 u16 *reflection_target = &fpga->reflection_low;
  97 #else
  98                 u16 *reflection_target = &fpga->reflection_high;
  99 #endif
 100                 /*
 101                  * wait for fpga out of reset
 102                  */
 103                 ctr = 0;
 104                 while (1) {
 105                         out_le16(&fpga->reflection_low,
 106                                 REFLECTION_TESTPATTERN);
 107
 108                         if (in_le16(reflection_target) ==
 109                                 REFLECTION_TESTPATTERN_INV)
 110                                 break;
 111
 112                         udelay(100000);
 113                         if (ctr++ > 5) {
 114                                 gd->arch.fpga_state[k] |=
 115                                         FPGA_STATE_REFLECTION_FAILED;
 116                                 break;
 117                         }
 118                 }
 119         }
 120
 121         return 0;
 122 }