board/gdsys/405ep/405ep.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <asm/ppc4xx-gpio.h>
  29 #include <asm/global_data.h>
  30
  31 #include "405ep.h"
  32 #include <gdsys_fpga.h>
  33
  34 #define REFLECTION_TESTPATTERN 0xdede
  35 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 int get_fpga_state(unsigned dev)
  40 {
  41         return gd->fpga_state[dev];
  42 }
  43
  44 void print_fpga_state(unsigned dev)
  45 {
  46         if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
  47                 puts("       Waiting for FPGA-DONE timed out.\n");
  48         if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
  49                 puts("       FPGA reflection test failed.\n");
  50 }
  51
  52 int board_early_init_f(void)
  53 {
  54         unsigned k;
  55
  56         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  57                 gd->fpga_state[k] = 0;
  58
  59         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  60         mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
  61         mtdcr(UIC0CR, 0x00000000);      /* set all to be non-critical */
  62         mtdcr(UIC0PR, 0xFFFFFF80);      /* set int polarities */
  63         mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
  64         mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest prio */
  65         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  66
  67         /*
  68          * EBC Configuration Register: set ready timeout to 512 ebc-clks
  69          * -> ca. 15 us
  70          */
  71         mtebc(EBC0_CFG, 0xa8400000);    /* ebc always driven */
  72         return 0;
  73 }
  74
  75 int board_early_init_r(void)
  76 {
  77         unsigned k;
  78         unsigned ctr;
  79
  80         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  81                 gd->fpga_state[k] = 0;
  82
  83         /*
  84          * reset FPGA
  85          */
  86         gd405ep_init();
  87
  88         gd405ep_set_fpga_reset(1);
  89
  90         gd405ep_setup_hw();
  91
  92         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  93                 ctr = 0;
  94                 while (!gd405ep_get_fpga_done(k)) {
  95                         udelay(100000);
  96                         if (ctr++ > 5) {
  97                                 gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
  98                                 break;
  99                         }
 100                 }
 101         }
 102
 103         udelay(10);
 104
 105         gd405ep_set_fpga_reset(0);
 106
 107         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
 108                 struct ihs_fpga *fpga =
 109                         (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
 110 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
 111                 u16 *reflection_target = &fpga->reflection_low;
 112 #else
 113                 u16 *reflection_target = &fpga->reflection_high;
 114 #endif
 115                 /*
 116                  * wait for fpga out of reset
 117                  */
 118                 ctr = 0;
 119                 while (1) {
 120                         out_le16(&fpga->reflection_low,
 121                                 REFLECTION_TESTPATTERN);
 122
 123                         if (in_le16(reflection_target) ==
 124                                 REFLECTION_TESTPATTERN_INV)
 125                                 break;
 126
 127                         udelay(100000);
 128                         if (ctr++ > 5) {
 129                                 gd->fpga_state[k] |=
 130                                         FPGA_STATE_REFLECTION_FAILED;
 131                                 break;
 132                         }
 133                 }
 134         }
 135
 136         return 0;
 137 }