board/gateworks/venice/venice.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2021 Gateworks Corporation
   4  */
   5
   6 #include <fdt_support.h>
   7 #include <init.h>
   8 #include <led.h>
   9 #include <miiphy.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/sys_proto.h>
  12
  13 #include "eeprom.h"
  14
  15 int board_phys_sdram_size(phys_size_t *size)
  16 {
  17         if (!size)
  18                 return -EINVAL;
  19
  20         *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  21
  22         return 0;
  23 }
  24
  25 int board_fit_config_name_match(const char *name)
  26 {
  27         int i  = 0;
  28         const char *dtb;
  29         static char init;
  30         char buf[32];
  31
  32         do {
  33                 dtb = eeprom_get_dtb_name(i++, buf, sizeof(buf));
  34                 if (!strcmp(dtb, name)) {
  35                         if (!init++)
  36                                 printf("DTB     : %s\n", name);
  37                         return 0;
  38                 }
  39         } while (dtb);
  40
  41         return -1;
  42 }
  43
  44 #if (IS_ENABLED(CONFIG_NET))
  45 static int setup_fec(void)
  46 {
  47         struct iomuxc_gpr_base_regs *gpr =
  48                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  49
  50 #ifndef CONFIG_IMX8MP
  51         /* Use 125M anatop REF_CLK1 for ENET1, not from external */
  52         clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
  53 #else
  54         /* Enable RGMII TX clk output */
  55         setbits_le32(&gpr->gpr[1], BIT(22));
  56 #endif
  57
  58         return 0;
  59 }
  60
  61 static int setup_eqos(void)
  62 {
  63         struct iomuxc_gpr_base_regs *gpr =
  64                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  65
  66         /* set INTF as RGMII, enable RGMII TXC clock */
  67         clrsetbits_le32(&gpr->gpr[1],
  68                         IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
  69         setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
  70
  71         return set_clk_eqos(ENET_125MHZ);
  72 }
  73
  74 int board_phy_config(struct phy_device *phydev)
  75 {
  76         unsigned short val;
  77         ofnode node;
  78
  79         switch (phydev->phy_id) {
  80         case 0x2000a231: /* TI DP83867 GbE PHY */
  81                 puts("DP83867 ");
  82                 /* LED configuration */
  83                 val = 0;
  84                 val |= 0x5 << 4; /* LED1(Amber;Speed)   : 1000BT link */
  85                 val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
  86                 phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
  87                 break;
  88         case 0xd565a401: /* MaxLinear GPY111 */
  89                 puts("GPY111 ");
  90                 node = phy_get_ofnode(phydev);
  91                 if (ofnode_valid(node)) {
  92                         u32 rx_delay, tx_delay;
  93
  94                         rx_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", 2000);
  95                         tx_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", 2000);
  96                         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x17);
  97                         val &= ~((0x7 << 12) | (0x7 << 8));
  98                         val |= (rx_delay / 500) << 12;
  99                         val |= (tx_delay / 500) << 8;
 100                         phy_write(phydev, MDIO_DEVAD_NONE, 0x17, val);
 101                 }
 102                 break;
 103         }
 104
 105         if (phydev->drv->config)
 106                 phydev->drv->config(phydev);
 107
 108         return 0;
 109 }
 110 #endif // IS_ENABLED(CONFIG_NET)
 111
 112 int board_init(void)
 113 {
 114         venice_eeprom_init(1);
 115
 116         if (IS_ENABLED(CONFIG_FEC_MXC))
 117                 setup_fec();
 118         if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
 119                 setup_eqos();
 120
 121         return 0;
 122 }
 123
 124 int board_late_init(void)
 125 {
 126         const char *str;
 127         char env[32];
 128         int ret, i;
 129         u8 enetaddr[6];
 130         char fdt[64];
 131
 132         /* Set board serial/model */
 133         if (!env_get("serial#"))
 134                 env_set_ulong("serial#", eeprom_get_serial());
 135         env_set("model", eeprom_get_model());
 136
 137         /* Set fdt_file vars */
 138         i = 0;
 139         do {
 140                 str = eeprom_get_dtb_name(i, fdt, sizeof(fdt));
 141                 if (str) {
 142                         sprintf(env, "fdt_file%d", i + 1);
 143                         strcat(fdt, ".dtb");
 144                         env_set(env, fdt);
 145                 }
 146                 i++;
 147         } while (str);
 148
 149         /* Set mac addrs */
 150         i = 0;
 151         do {
 152                 if (i)
 153                         sprintf(env, "eth%daddr", i);
 154                 else
 155                         sprintf(env, "ethaddr");
 156                 str = env_get(env);
 157                 if (!str) {
 158                         ret = eeprom_getmac(i, enetaddr);
 159                         if (!ret)
 160                                 eth_env_set_enetaddr(env, enetaddr);
 161                 }
 162                 i++;
 163         } while (!ret);
 164
 165         return 0;
 166 }
 167
 168 int board_mmc_get_env_dev(int devno)
 169 {
 170         return devno;
 171 }
 172
 173 int ft_board_setup(void *fdt, struct bd_info *bd)
 174 {
 175         const char *base_model = eeprom_get_baseboard_model();
 176         char pcbrev;
 177         int off;
 178
 179         /* set board model dt prop */
 180         fdt_setprop_string(fdt, 0, "board", eeprom_get_model());
 181
 182         if (!strncmp(base_model, "GW73", 4)) {
 183                 pcbrev = get_pcb_rev(base_model);
 184
 185                 if (pcbrev > 'B') {
 186                         printf("adjusting dt for %s\n", base_model);
 187
 188                         /*
 189                          * revC replaced PCIe 5-port switch with 4-port
 190                          * which changed ethernet1 PCIe GbE
 191                          * from: pcie@0,0/pcie@1,0/pcie@2,4/pcie@6.0
 192                          *   to: pcie@0,0/pcie@1,0/pcie@2,3/pcie@5.0
 193                          */
 194                         off = fdt_path_offset(fdt, "ethernet1");
 195                         if (off > 0) {
 196                                 u32 reg[5];
 197
 198                                 fdt_set_name(fdt, off, "pcie@5,0");
 199                                 off = fdt_parent_offset(fdt, off);
 200                                 fdt_set_name(fdt, off, "pcie@2,3");
 201                                 memset(reg, 0, sizeof(reg));
 202                                 reg[0] = cpu_to_fdt32(PCI_DEVFN(3, 0));
 203                                 fdt_setprop(fdt, off, "reg", reg, sizeof(reg));
 204                         }
 205                 }
 206         }
 207
 208         return 0;
 209 }