1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2021 Gateworks Corporation
9 #include <asm/arch/clock.h>
10 #include <asm/arch/sys_proto.h>
14 int board_phys_sdram_size(phys_size_t *size)
19 *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
24 int board_fit_config_name_match(const char *name)
32 dtb = eeprom_get_dtb_name(i++, buf, sizeof(buf));
33 if (!strcmp(dtb, name)) {
35 printf("DTB : %s\n", name);
43 #if (IS_ENABLED(CONFIG_NET))
44 static int setup_fec(void)
46 struct iomuxc_gpr_base_regs *gpr =
47 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
50 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
51 clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
53 /* Enable RGMII TX clk output */
54 setbits_le32(&gpr->gpr[1], BIT(22));
60 static int setup_eqos(void)
62 struct iomuxc_gpr_base_regs *gpr =
63 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
65 /* set INTF as RGMII, enable RGMII TXC clock */
66 clrsetbits_le32(&gpr->gpr[1],
67 IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
68 setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
70 return set_clk_eqos(ENET_125MHZ);
73 int board_phy_config(struct phy_device *phydev)
78 switch (phydev->phy_id) {
79 case 0x2000a231: /* TI DP83867 GbE PHY */
81 /* LED configuration */
83 val |= 0x5 << 4; /* LED1(Amber;Speed) : 1000BT link */
84 val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
85 phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
87 case 0xd565a401: /* MaxLinear GPY111 */
89 node = phy_get_ofnode(phydev);
90 if (ofnode_valid(node)) {
91 u32 rx_delay, tx_delay;
93 rx_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", 2000);
94 tx_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", 2000);
95 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x17);
96 val &= ~((0x7 << 12) | (0x7 << 8));
97 val |= (rx_delay / 500) << 12;
98 val |= (tx_delay / 500) << 8;
99 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, val);
104 if (phydev->drv->config)
105 phydev->drv->config(phydev);
109 #endif // IS_ENABLED(CONFIG_NET)
115 if (IS_ENABLED(CONFIG_FEC_MXC))
117 if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
123 int board_late_init(void)
133 /* Set board serial/model */
134 if (!env_get("serial#"))
135 env_set_ulong("serial#", eeprom_get_serial());
136 env_set("model", eeprom_get_model());
138 /* Set fdt_file vars */
141 str = eeprom_get_dtb_name(i, fdt, sizeof(fdt));
143 sprintf(env, "fdt_file%d", i + 1);
154 sprintf(env, "eth%daddr", i);
156 sprintf(env, "ethaddr");
159 ret = eeprom_getmac(i, enetaddr);
161 eth_env_set_enetaddr(env, enetaddr);
169 int board_mmc_get_env_dev(int devno)
174 int ft_board_setup(void *blob, struct bd_info *bd)
178 /* set board model dt prop */
179 fdt_setprop_string(blob, 0, "board", eeprom_get_model());
181 /* update temp thresholds */
182 off = fdt_path_offset(blob, "/thermal-zones/cpu-thermal/trips");
184 int minc, maxc, prop;
186 get_cpu_temp_grade(&minc, &maxc);
187 fdt_for_each_subnode(prop, blob, off) {
188 const char *type = fdt_getprop(blob, prop, "type", NULL);
190 if (type && (!strcmp("critical", type)))
191 fdt_setprop_u32(blob, prop, "temperature", maxc * 1000);
192 else if (type && (!strcmp("passive", type)))
193 fdt_setprop_u32(blob, prop, "temperature", (maxc - 10) * 1000);