board/gateworks/venice/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2021 Gateworks Corporation
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <hang.h>
   9 #include <i2c.h>
  10 #include <image.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <spl.h>
  14 #include <asm/io.h>
  15 #include <asm/mach-imx/gpio.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/imx8mm_pins.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/mach-imx/boot_mode.h>
  21 #include <asm/arch/ddr.h>
  22 #include <asm-generic/gpio.h>
  23
  24 #include <dm/uclass.h>
  25 #include <dm/device.h>
  26 #include <dm/uclass-internal.h>
  27 #include <dm/device-internal.h>
  28
  29 #include <power/bd71837.h>
  30 #include <power/mp5416.h>
  31
  32 #include "gsc.h"
  33 #include "lpddr4_timing.h"
  34
  35 #define PCIE_RSTN IMX_GPIO_NR(4, 6)
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 static void spl_dram_init(int size)
  40 {
  41         struct dram_timing_info *dram_timing;
  42
  43         switch (size) {
  44         case 1:
  45                 dram_timing = &dram_timing_1gb;
  46                 break;
  47         case 2:
  48                 dram_timing = &dram_timing_2gb;
  49                 break;
  50         case 4:
  51                 dram_timing = &dram_timing_4gb;
  52                 break;
  53         default:
  54                 printf("Unknown DDR configuration: %d GiB\n", size);
  55                 dram_timing = &dram_timing_1gb;
  56                 size = 1;
  57         }
  58
  59         printf("DRAM    : LPDDR4 %d GiB\n", size);
  60         ddr_init(dram_timing);
  61         writel(size, M4_BOOTROM_BASE_ADDR);
  62 }
  63
  64 #define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  65 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  66
  67 static iomux_v3_cfg_t const uart_pads[] = {
  68         IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  69         IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  70 };
  71
  72 static iomux_v3_cfg_t const wdog_pads[] = {
  73         IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  74 };
  75
  76 int board_early_init_f(void)
  77 {
  78         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  79
  80         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  81
  82         set_wdog_reset(wdog);
  83
  84         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  85
  86         return 0;
  87 }
  88
  89 /*
  90  * Model specific PMIC adjustments necessary prior to DRAM init
  91  *
  92  * Note that we can not use pmic dm drivers here as we have a generic
  93  * venice dt that does not have board-specific pmic's defined.
  94  *
  95  * Instead we must use dm_i2c so we a helpers to give us
  96  * clrsetbit functions we would otherwise have if we could use PMIC dm
  97  * drivers.
  98  */
  99 static int dm_i2c_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set)
 100 {
 101         int ret;
 102         u8 val;
 103
 104         ret = dm_i2c_read(dev, reg, &val, 1);
 105         if (ret)
 106                 return ret;
 107         val = (val & ~clr) | set;
 108
 109         return dm_i2c_write(dev, reg, &val, 1);
 110 }
 111
 112 static int power_init_board(void)
 113 {
 114         const char *model = gsc_get_model();
 115         struct udevice *bus;
 116         struct udevice *dev;
 117         int ret;
 118
 119         if ((!strncmp(model, "GW71", 4)) ||
 120             (!strncmp(model, "GW72", 4)) ||
 121             (!strncmp(model, "GW73", 4))) {
 122                 ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
 123                 if (ret) {
 124                         printf("PMIC    : failed I2C1 probe: %d\n", ret);
 125                         return ret;
 126                 }
 127                 ret = dm_i2c_probe(bus, 0x69, 0, &dev);
 128                 if (ret) {
 129                         printf("PMIC    : failed probe: %d\n", ret);
 130                         return ret;
 131                 }
 132                 puts("PMIC    : MP5416\n");
 133
 134                 /* set VDD_ARM SW3 to 0.92V for 1.6GHz */
 135                 dm_i2c_reg_write(dev, MP5416_VSET_SW3,
 136                                  BIT(7) | MP5416_VSET_SW3_SVAL(920000));
 137         }
 138
 139         else if ((!strncmp(model, "GW7901", 6)) ||
 140                  (!strncmp(model, "GW7902", 6))) {
 141                 if (!strncmp(model, "GW7901", 6))
 142                         ret = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
 143                 else
 144                         ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
 145                 if (ret) {
 146                         printf("PMIC    : failed I2C2 probe: %d\n", ret);
 147                         return ret;
 148                 }
 149                 ret = dm_i2c_probe(bus, 0x4b, 0, &dev);
 150                 if (ret) {
 151                         printf("PMIC    : failed probe: %d\n", ret);
 152                         return ret;
 153                 }
 154                 puts("PMIC    : BD71847\n");
 155
 156                 /* unlock the PMIC regs */
 157                 dm_i2c_reg_write(dev, BD718XX_REGLOCK, 0x1);
 158
 159                 /* set switchers to forced PWM mode */
 160                 dm_i2c_clrsetbits(dev, BD718XX_BUCK1_CTRL, 0, 0x8);
 161                 dm_i2c_clrsetbits(dev, BD718XX_BUCK2_CTRL, 0, 0x8);
 162                 dm_i2c_clrsetbits(dev, BD718XX_1ST_NODVS_BUCK_CTRL, 0, 0x8);
 163                 dm_i2c_clrsetbits(dev, BD718XX_2ND_NODVS_BUCK_CTRL, 0, 0x8);
 164                 dm_i2c_clrsetbits(dev, BD718XX_3RD_NODVS_BUCK_CTRL, 0, 0x8);
 165                 dm_i2c_clrsetbits(dev, BD718XX_4TH_NODVS_BUCK_CTRL, 0, 0x8);
 166
 167                 /* increase VDD_0P95 (VDD_GPU/VPU/DRAM) to 0.975v for 1.5Ghz DDR */
 168                 dm_i2c_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
 169
 170                 /* increase VDD_SOC to 0.85v before first DRAM access */
 171                 dm_i2c_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
 172
 173                 /* increase VDD_ARM to 0.92v for 800 and 1600Mhz */
 174                 dm_i2c_reg_write(dev, BD718XX_BUCK2_VOLT_RUN, 0x16);
 175
 176                 /* Lock the PMIC regs */
 177                 dm_i2c_reg_write(dev, BD718XX_REGLOCK, 0x11);
 178         }
 179
 180         return 0;
 181 }
 182
 183 void board_init_f(ulong dummy)
 184 {
 185         struct udevice *dev;
 186         int ret;
 187         int dram_sz;
 188
 189         arch_cpu_init();
 190
 191         init_uart_clk(1);
 192
 193         board_early_init_f();
 194
 195         timer_init();
 196
 197         preloader_console_init();
 198
 199         /* Clear the BSS. */
 200         memset(__bss_start, 0, __bss_end - __bss_start);
 201
 202         ret = spl_early_init();
 203         if (ret) {
 204                 debug("spl_early_init() failed: %d\n", ret);
 205                 hang();
 206         }
 207
 208         ret = uclass_get_device_by_name(UCLASS_CLK,
 209                                         "clock-controller@30380000",
 210                                         &dev);
 211         if (ret < 0) {
 212                 printf("Failed to find clock node. Check device tree\n");
 213                 hang();
 214         }
 215
 216         enable_tzc380();
 217
 218         /* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */
 219         gpio_request(PCIE_RSTN, "perst#");
 220         gpio_direction_output(PCIE_RSTN, 0);
 221
 222         /* GSC */
 223         dram_sz = gsc_init(0);
 224
 225         /* PMIC */
 226         power_init_board();
 227
 228         /* DDR initialization */
 229         spl_dram_init(dram_sz);
 230
 231         board_init_r(NULL, 0);
 232 }
 233
 234 /* determine prioritized order of boot devices to load U-Boot from */
 235 void board_boot_order(u32 *spl_boot_list)
 236 {
 237         /*
 238          * If the SPL was loaded via serial loader, we try to get
 239          * U-Boot proper via USB SDP.
 240          */
 241         if (spl_boot_device() == BOOT_DEVICE_BOARD)
 242                 spl_boot_list[0] = BOOT_DEVICE_BOARD;
 243
 244         /* we have only eMMC in default venice dt */
 245         spl_boot_list[0] = BOOT_DEVICE_MMC1;
 246 }
 247
 248 /* return boot device based on where the SPL was loaded from */
 249 int spl_board_boot_device(enum boot_device boot_dev_spl)
 250 {
 251         switch (boot_dev_spl) {
 252         case USB_BOOT:
 253                 return BOOT_DEVICE_BOARD;
 254         /* SDHC2 */
 255         case SD2_BOOT:
 256         case MMC2_BOOT:
 257                 return BOOT_DEVICE_MMC1;
 258         /* SDHC3 */
 259         case SD3_BOOT:
 260         case MMC3_BOOT:
 261                 return BOOT_DEVICE_MMC2;
 262         default:
 263                 return BOOT_DEVICE_NONE;
 264         }
 265 }