board/gateworks/venice/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2021 Gateworks Corporation
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <hang.h>
   9 #include <i2c.h>
  10 #include <image.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <spl.h>
  14 #include <asm/io.h>
  15 #include <asm/mach-imx/gpio.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/imx8mm_pins.h>
  19 #include <asm/arch/imx8mn_pins.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/mach-imx/boot_mode.h>
  22 #include <asm/arch/ddr.h>
  23 #include <asm-generic/gpio.h>
  24
  25 #include <dm/uclass.h>
  26 #include <dm/device.h>
  27 #include <dm/uclass-internal.h>
  28 #include <dm/device-internal.h>
  29
  30 #include <power/bd71837.h>
  31 #include <power/mp5416.h>
  32
  33 #include "gsc.h"
  34 #include "lpddr4_timing.h"
  35
  36 #define PCIE_RSTN IMX_GPIO_NR(4, 6)
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 static void spl_dram_init(int size)
  41 {
  42         struct dram_timing_info *dram_timing;
  43
  44         switch (size) {
  45 #ifdef CONFIG_IMX8MM
  46         case 1:
  47                 dram_timing = &dram_timing_1gb;
  48                 break;
  49         case 2:
  50                 dram_timing = &dram_timing_2gb;
  51                 break;
  52         case 4:
  53                 dram_timing = &dram_timing_4gb;
  54                 break;
  55         default:
  56                 printf("Unknown DDR configuration: %d GiB\n", size);
  57                 dram_timing = &dram_timing_1gb;
  58                 size = 1;
  59 #endif
  60 #ifdef CONFIG_IMX8MN
  61         case 1:
  62                 dram_timing = &dram_timing_1gb_single_die;
  63                 break;
  64         case 2:
  65                 if (!strcmp(gsc_get_model(), "GW7902-SP466-A") ||
  66                     !strcmp(gsc_get_model(), "GW7902-SP466-B")) {
  67                         dram_timing = &dram_timing_2gb_dual_die;
  68                 } else {
  69                         dram_timing = &dram_timing_2gb_single_die;
  70                 }
  71                 break;
  72         default:
  73                 printf("Unknown DDR configuration: %d GiB\n", size);
  74                 dram_timing = &dram_timing_2gb_dual_die;
  75                 size = 2;
  76 #endif
  77         }
  78
  79         printf("DRAM    : LPDDR4 %d GiB\n", size);
  80         ddr_init(dram_timing);
  81 }
  82
  83 #define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  84 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  85
  86 #ifdef CONFIG_IMX8MM
  87 static iomux_v3_cfg_t const uart_pads[] = {
  88         IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  89         IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  90 };
  91
  92 static iomux_v3_cfg_t const wdog_pads[] = {
  93         IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  94 };
  95 #endif
  96 #ifdef CONFIG_IMX8MN
  97 static const iomux_v3_cfg_t uart_pads[] = {
  98         IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  99         IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 100 };
 101
 102 static const iomux_v3_cfg_t wdog_pads[] = {
 103         IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 104 };
 105 #endif
 106
 107 int board_early_init_f(void)
 108 {
 109         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 110
 111         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 112
 113         set_wdog_reset(wdog);
 114
 115         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 116
 117         return 0;
 118 }
 119
 120 /*
 121  * Model specific PMIC adjustments necessary prior to DRAM init
 122  *
 123  * Note that we can not use pmic dm drivers here as we have a generic
 124  * venice dt that does not have board-specific pmic's defined.
 125  *
 126  * Instead we must use dm_i2c so we a helpers to give us
 127  * clrsetbit functions we would otherwise have if we could use PMIC dm
 128  * drivers.
 129  */
 130 static int dm_i2c_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set)
 131 {
 132         int ret;
 133         u8 val;
 134
 135         ret = dm_i2c_read(dev, reg, &val, 1);
 136         if (ret)
 137                 return ret;
 138         val = (val & ~clr) | set;
 139
 140         return dm_i2c_write(dev, reg, &val, 1);
 141 }
 142
 143 static int power_init_board(void)
 144 {
 145         const char *model = gsc_get_model();
 146         struct udevice *bus;
 147         struct udevice *dev;
 148         int ret;
 149
 150         if ((!strncmp(model, "GW71", 4)) ||
 151             (!strncmp(model, "GW72", 4)) ||
 152             (!strncmp(model, "GW73", 4))) {
 153                 ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
 154                 if (ret) {
 155                         printf("PMIC    : failed I2C1 probe: %d\n", ret);
 156                         return ret;
 157                 }
 158                 ret = dm_i2c_probe(bus, 0x69, 0, &dev);
 159                 if (ret) {
 160                         printf("PMIC    : failed probe: %d\n", ret);
 161                         return ret;
 162                 }
 163                 puts("PMIC    : MP5416\n");
 164
 165                 /* set VDD_ARM SW3 to 0.92V for 1.6GHz */
 166                 dm_i2c_reg_write(dev, MP5416_VSET_SW3,
 167                                  BIT(7) | MP5416_VSET_SW3_SVAL(920000));
 168         }
 169
 170         else if ((!strncmp(model, "GW7901", 6)) ||
 171                  (!strncmp(model, "GW7902", 6))) {
 172                 if (!strncmp(model, "GW7901", 6))
 173                         ret = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
 174                 else
 175                         ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
 176                 if (ret) {
 177                         printf("PMIC    : failed I2C2 probe: %d\n", ret);
 178                         return ret;
 179                 }
 180                 ret = dm_i2c_probe(bus, 0x4b, 0, &dev);
 181                 if (ret) {
 182                         printf("PMIC    : failed probe: %d\n", ret);
 183                         return ret;
 184                 }
 185                 puts("PMIC    : BD71847\n");
 186
 187                 /* unlock the PMIC regs */
 188                 dm_i2c_reg_write(dev, BD718XX_REGLOCK, 0x1);
 189
 190                 /* set switchers to forced PWM mode */
 191                 dm_i2c_clrsetbits(dev, BD718XX_BUCK1_CTRL, 0, 0x8);
 192                 dm_i2c_clrsetbits(dev, BD718XX_BUCK2_CTRL, 0, 0x8);
 193                 dm_i2c_clrsetbits(dev, BD718XX_1ST_NODVS_BUCK_CTRL, 0, 0x8);
 194                 dm_i2c_clrsetbits(dev, BD718XX_2ND_NODVS_BUCK_CTRL, 0, 0x8);
 195                 dm_i2c_clrsetbits(dev, BD718XX_3RD_NODVS_BUCK_CTRL, 0, 0x8);
 196                 dm_i2c_clrsetbits(dev, BD718XX_4TH_NODVS_BUCK_CTRL, 0, 0x8);
 197
 198                 /* increase VDD_0P95 (VDD_GPU/VPU/DRAM) to 0.975v for 1.5Ghz DDR */
 199                 dm_i2c_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
 200
 201                 /* increase VDD_SOC to 0.85v before first DRAM access */
 202                 dm_i2c_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
 203
 204                 /* increase VDD_ARM to 0.92v for 800 and 1600Mhz */
 205                 dm_i2c_reg_write(dev, BD718XX_BUCK2_VOLT_RUN, 0x16);
 206
 207                 /* Lock the PMIC regs */
 208                 dm_i2c_reg_write(dev, BD718XX_REGLOCK, 0x11);
 209         }
 210
 211         return 0;
 212 }
 213
 214 void board_init_f(ulong dummy)
 215 {
 216         struct udevice *dev;
 217         int ret;
 218         int dram_sz;
 219
 220         arch_cpu_init();
 221
 222         init_uart_clk(1);
 223
 224         board_early_init_f();
 225
 226         timer_init();
 227
 228         preloader_console_init();
 229
 230         /* Clear the BSS. */
 231         memset(__bss_start, 0, __bss_end - __bss_start);
 232
 233         ret = spl_early_init();
 234         if (ret) {
 235                 debug("spl_early_init() failed: %d\n", ret);
 236                 hang();
 237         }
 238
 239         ret = uclass_get_device_by_name(UCLASS_CLK,
 240                                         "clock-controller@30380000",
 241                                         &dev);
 242         if (ret < 0) {
 243                 printf("Failed to find clock node. Check device tree\n");
 244                 hang();
 245         }
 246
 247         enable_tzc380();
 248
 249         /* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */
 250         gpio_request(PCIE_RSTN, "perst#");
 251         gpio_direction_output(PCIE_RSTN, 0);
 252
 253         /* GSC */
 254         dram_sz = gsc_init(0);
 255
 256         /* PMIC */
 257         power_init_board();
 258
 259         /* DDR initialization */
 260         spl_dram_init(dram_sz);
 261
 262         board_init_r(NULL, 0);
 263 }
 264
 265 /* determine prioritized order of boot devices to load U-Boot from */
 266 void board_boot_order(u32 *spl_boot_list)
 267 {
 268         /*
 269          * If the SPL was loaded via serial loader, we try to get
 270          * U-Boot proper via USB SDP.
 271          */
 272         if (spl_boot_device() == BOOT_DEVICE_BOARD)
 273                 spl_boot_list[0] = BOOT_DEVICE_BOARD;
 274
 275         /* we have only eMMC in default venice dt */
 276         spl_boot_list[0] = BOOT_DEVICE_MMC1;
 277 }
 278
 279 /* return boot device based on where the SPL was loaded from */
 280 int spl_board_boot_device(enum boot_device boot_dev_spl)
 281 {
 282         switch (boot_dev_spl) {
 283         case USB_BOOT:
 284                 return BOOT_DEVICE_BOARD;
 285         /* SDHC2 */
 286         case SD2_BOOT:
 287         case MMC2_BOOT:
 288                 return BOOT_DEVICE_MMC1;
 289         /* SDHC3 */
 290         case SD3_BOOT:
 291         case MMC3_BOOT:
 292                 return BOOT_DEVICE_MMC2;
 293         default:
 294                 return BOOT_DEVICE_NONE;
 295         }
 296 }