1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2021 Gateworks Corporation
9 #include <linux/delay.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 int board_phys_sdram_size(phys_size_t *size)
23 int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
25 if (ddr_size == 0x4) {
27 } else if (ddr_size == 0x3) {
29 } else if (ddr_size == 0x2) {
31 } else if (ddr_size == 0x1) {
34 printf("Unknown DDR type!!!\n");
41 int board_fit_config_name_match(const char *name)
48 dtb = gsc_get_dtb_name(i++, buf, sizeof(buf));
49 if (!strcmp(dtb, name))
56 #if (IS_ENABLED(CONFIG_FEC_MXC))
57 static int setup_fec(void)
59 struct iomuxc_gpr_base_regs *gpr =
60 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
62 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
63 clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
68 int board_phy_config(struct phy_device *phydev)
72 switch (phydev->phy_id) {
73 case 0x2000a231: /* TI DP83867 GbE PHY */
75 /* LED configuration */
77 val |= 0x5 << 4; /* LED1(Amber;Speed) : 1000BT link */
78 val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
79 phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
83 if (phydev->drv->config)
84 phydev->drv->config(phydev);
88 #endif // IS_ENABLED(CONFIG_FEC_MXC)
94 if (IS_ENABLED(CONFIG_FEC_MXC))
102 int board_late_init(void)
115 sprintf(env, "eth%daddr", i);
117 sprintf(env, "ethaddr");
118 ethmac = env_get(env);
120 ret = gsc_getmac(i, enetaddr);
122 eth_env_set_enetaddr(env, enetaddr);
130 int board_mmc_get_env_dev(int devno)