1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Gateworks Corporation
5 * Author: Tim Harvey <tharvey@gateworks.com>
10 #include <fdt_support.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/arch/mx6-pins.h>
19 #include <asm/arch/mxc_hdmi.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/mach-imx/boot_mode.h>
22 #include <asm/mach-imx/video.h>
23 #include <jffs2/load_kernel.h>
24 #include <linux/ctype.h>
25 #include <linux/delay.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 /* configure eth0 PHY board-specific LED behavior */
32 int board_phy_config(struct phy_device *phydev)
37 switch (phydev->phy_id) {
41 * Page 3, Register 16: LED[2:0] Function Control Register
42 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
43 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
45 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
46 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
49 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
50 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
54 /* LED configuration */
56 val |= 0x5 << 4; /* LED1(Amber;Speed) : 1000BT link */
57 val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
58 phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
60 /* configure register 0x170 for ref CLKOUT */
61 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
62 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
63 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
64 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
66 val |= 0x0b00; /* chD tx clock*/
67 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
71 node = phy_get_ofnode(phydev);
72 if (ofnode_valid(node)) {
73 u32 rx_delay, tx_delay;
75 rx_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", 2000);
76 tx_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", 2000);
77 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x17);
78 val &= ~((0x7 << 12) | (0x7 << 8));
79 val |= (rx_delay / 500) << 12;
80 val |= (tx_delay / 500) << 8;
81 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, val);
86 /* Fixed PHY: for GW5904/GW5909 this is Marvell 88E6176 GbE Switch */
87 if (phydev->phy_id == PHY_FIXED_ID &&
88 (board_type == GW5904 || board_type == GW5909)) {
89 struct mii_dev *bus = miiphy_get_dev_by_name("mdio");
92 /* GPIO[0] output CLK125 for RGMII_REFCLK */
93 bus->write(bus, 0x1c, 0, 0x1a, (1 << 15) | (0x62 << 8) | 0xfe);
94 bus->write(bus, 0x1c, 0, 0x1a, (1 << 15) | (0x68 << 8) | 7);
96 /* Port 0-3 LED configuration: Table 80/82 */
97 /* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
98 bus->write(bus, 0x10, 0, 0x16, 0x8088);
99 bus->write(bus, 0x11, 0, 0x16, 0x8088);
100 bus->write(bus, 0x12, 0, 0x16, 0x8088);
101 bus->write(bus, 0x13, 0, 0x16, 0x8088);
104 if (phydev->drv->config)
105 phydev->drv->config(phydev);
110 #if defined(CONFIG_VIDEO_IPUV3)
111 static void enable_hdmi(struct display_info_t const *dev)
113 imx_enable_hdmi_phy();
116 static int detect_lvds(struct display_info_t const *dev)
118 /* only the following boards support LVDS connectors */
119 switch (board_type) {
131 return (i2c_get_dev(dev->bus, dev->addr) ? 1 : 0);
134 static void enable_lvds(struct display_info_t const *dev)
136 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
138 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
139 u32 reg = readl(&iomux->gpr[2]);
140 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
141 writel(reg, &iomux->gpr[2]);
144 switch (board_type) {
148 if (!strncmp(dev->mode.name, "Hannstar", 8)) {
149 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
150 gpio_request(IMX_GPIO_NR(1, 10), "cabc");
151 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
152 } else if (!strncmp(dev->mode.name, "DLC", 3)) {
153 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
154 gpio_request(IMX_GPIO_NR(1, 10), "touch_rst#");
155 gpio_direction_output(IMX_GPIO_NR(1, 10), 1);
162 /* Configure backlight */
163 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
164 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
165 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
168 struct display_info_t const displays[] = {{
172 .pixfmt = IPU_PIX_FMT_RGB24,
173 .detect = detect_hdmi,
174 .enable = enable_hdmi,
188 .vmode = FB_VMODE_NONINTERLACED
190 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
193 .pixfmt = IPU_PIX_FMT_LVDS666,
194 .detect = detect_lvds,
195 .enable = enable_lvds,
197 .name = "Hannstar-XGA",
209 .vmode = FB_VMODE_NONINTERLACED
214 .detect = detect_lvds,
215 .enable = enable_lvds,
216 .pixfmt = IPU_PIX_FMT_LVDS666,
218 .name = "DLC700JMGT4",
220 .xres = 1024, /* 1024x600active pixels */
222 .pixclock = 15385, /* 64MHz */
230 .vmode = FB_VMODE_NONINTERLACED
232 /* DLC0700XDP21LF-C-1 */
235 .detect = detect_lvds,
236 .enable = enable_lvds,
237 .pixfmt = IPU_PIX_FMT_LVDS666,
239 .name = "DLC0700XDP21LF",
241 .xres = 1024, /* 1024x600active pixels */
243 .pixclock = 15385, /* 64MHz */
251 .vmode = FB_VMODE_NONINTERLACED
256 .detect = detect_lvds,
257 .enable = enable_lvds,
258 .pixfmt = IPU_PIX_FMT_LVDS666,
260 .name = "DLC800FIGT3",
262 .xres = 1024, /* 1024x768 active pixels */
264 .pixclock = 15385, /* 64MHz */
272 .vmode = FB_VMODE_NONINTERLACED
276 .detect = detect_lvds,
277 .enable = enable_lvds,
278 .pixfmt = IPU_PIX_FMT_LVDS666,
284 .pixclock = 15385, /* 64MHz */
292 .vmode = FB_VMODE_NONINTERLACED
296 size_t display_count = ARRAY_SIZE(displays);
298 static void setup_display(void)
300 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
301 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
306 /* Turn on LDB0,IPU,IPU DI0 clocks */
307 reg = __raw_readl(&mxc_ccm->CCGR3);
308 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
309 writel(reg, &mxc_ccm->CCGR3);
311 /* set LDB0, LDB1 clk select to 011/011 */
312 reg = readl(&mxc_ccm->cs2cdr);
313 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
314 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
315 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
316 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
317 writel(reg, &mxc_ccm->cs2cdr);
319 reg = readl(&mxc_ccm->cscmr2);
320 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
321 writel(reg, &mxc_ccm->cscmr2);
323 reg = readl(&mxc_ccm->chsccdr);
324 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
325 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
326 writel(reg, &mxc_ccm->chsccdr);
328 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
329 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
330 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
331 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
332 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
333 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
334 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
335 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
336 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
337 writel(reg, &iomux->gpr[2]);
339 reg = readl(&iomux->gpr[3]);
340 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
341 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
342 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
343 writel(reg, &iomux->gpr[3]);
345 #endif /* CONFIG_VIDEO_IPUV3 */
348 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
349 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
350 * properly and assert reset for 100ms.
352 #define MAX_PCI_DEVS 32
356 unsigned short vendor;
357 unsigned short device;
358 unsigned short class;
359 unsigned short busno; /* subbordinate busno */
360 struct pci_dev *ppar;
362 struct pci_dev pci_devs[MAX_PCI_DEVS];
366 void board_pci_fixup_dev(struct udevice *bus, struct udevice *udev)
368 struct pci_child_plat *pdata = dev_get_parent_plat(udev);
369 struct pci_dev *pdev = &pci_devs[pci_devno++];
370 unsigned short vendor = pdata->vendor;
371 unsigned short device = pdata->device;
372 unsigned int class = pdata->class;
373 pci_dev_t dev = dm_pci_get_bdf(udev);
376 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
377 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
379 /* store array of devs for later use in device-tree fixup */
382 pdev->vendor = vendor;
383 pdev->device = device;
386 if (class == PCI_CLASS_BRIDGE_PCI)
387 pdev->busno = ++pci_bridgeno;
391 /* fixup RC - it should be 00:00.0 not 00:01.0 */
392 if (PCI_BUS(dev) == 0)
395 /* find dev's parent */
396 for (i = 0; i < pci_devno; i++) {
397 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
398 pdev->ppar = &pci_devs[i];
403 /* assert downstream PERST# */
404 if (vendor == PCI_VENDOR_ID_PLX &&
405 (device & 0xfff0) == 0x8600 &&
406 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
408 debug("configuring PLX 860X downstream PERST#\n");
409 pci_bus_read_config(bus, dev, 0x62c, &val, PCI_SIZE_32);
410 val |= 0xaaa8; /* GPIO1-7 outputs */
411 pci_bus_write_config(bus, dev, 0x62c, val, PCI_SIZE_32);
413 pci_bus_read_config(bus, dev, 0x644, &val, PCI_SIZE_32);
414 val |= 0xfe; /* GPIO1-7 output high */
415 pci_bus_write_config(bus, dev, 0x644, val, PCI_SIZE_32);
421 #ifdef CONFIG_SERIAL_TAG
423 * called when setting up ATAGS before booting kernel
424 * populate serialnum from the following (in order of priority):
428 void get_board_serial(struct tag_serialnr *serialnr)
430 char *serial = env_get("serial#");
434 serialnr->low = dectoul(serial, NULL);
435 } else if (ventana_info.model[0]) {
437 serialnr->low = ventana_info.serial;
449 int board_early_init_f(void)
451 #if defined(CONFIG_VIDEO_IPUV3)
459 gd->ram_size = imx_ddr_size();
465 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
467 clrsetbits_le32(&iomuxc_regs->gpr[1],
468 IOMUXC_GPR1_OTG_ID_MASK,
469 IOMUXC_GPR1_OTG_ID_GPIO1);
471 /* address of linux boot parameters */
472 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
474 /* read Gateworks EEPROM into global struct (used later) */
475 board_type = read_eeprom(&ventana_info);
477 setup_iomux_gpio(board_type);
479 /* show GSC details */
480 run_command("gsc", 0);
485 int board_fit_config_name_match(const char *name)
493 dtb = gsc_get_dtb_name(i++, buf, sizeof(buf));
494 if (dtb && !strcmp(dtb, name)) {
496 printf("DTB: %s\n", name);
504 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
506 * called during late init (after relocation and after board_init())
507 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
512 struct ventana_board_info *info = &ventana_info;
514 int quiet; /* Quiet or minimal output mode */
517 p = env_get("quiet");
519 quiet = simple_strtol(p, NULL, 10);
521 env_set("quiet", "0");
523 puts("\nGateworks Corporation Copyright 2014\n");
524 if (info->model[0]) {
525 printf("Model: %s\n", info->model);
526 printf("MFGDate: %02x-%02x-%02x%02x\n",
527 info->mfgdate[0], info->mfgdate[1],
528 info->mfgdate[2], info->mfgdate[3]);
529 printf("Serial:%d\n", info->serial);
531 puts("Invalid EEPROM - board will not function fully\n");
540 #ifdef CONFIG_CMD_BMODE
542 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
543 * see Table 8-11 and Table 5-9
544 * BOOT_CFG1[7] = 1 (boot from NAND)
545 * BOOT_CFG1[5] = 0 - raw NAND
546 * BOOT_CFG1[4] = 0 - default pad settings
547 * BOOT_CFG1[3:2] = 00 - devices = 1
548 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
549 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
550 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
551 * BOOT_CFG2[0] = 0 - Reset time 12ms
553 static const struct boot_mode board_boot_modes[] = {
554 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
555 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
556 { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
557 { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
562 /* setup GPIO pinmux and default configuration per baseboard and env */
563 void setup_board_gpio(int board, struct ventana_board_info *info)
569 int quiet = simple_strtol(env_get("quiet"), NULL, 10);
571 if (board >= GW_UNKNOWN)
575 if (gpio_cfg[board].rs232_en) {
576 gpio_direction_output(gpio_cfg[board].rs232_en,
577 (hwconfig("rs232")) ? 0 : 1);
581 if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
582 gpio_direction_output(GP_MSATA_SEL,
583 (hwconfig("msata")) ? 1 : 0);
586 /* USBOTG Select (PCISKT or FrontPanel) */
587 if (gpio_cfg[board].usb_sel) {
588 gpio_direction_output(gpio_cfg[board].usb_sel,
589 (hwconfig("usb_pcisel")) ? 1 : 0);
593 * Configure DIO pinmux/padctl registers
594 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
596 for (i = 0; i < gpio_cfg[board].dio_num; i++) {
597 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
598 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
599 unsigned int cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
601 if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
603 sprintf(arg, "dio%d", i);
606 s = hwconfig_subarg(arg, "padctrl", &len);
608 ctrl = MUX_PAD_CTRL(hextoul(s, NULL)
609 & 0x1ffff) | MUX_MODE_SION;
611 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
613 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
614 (cfg->gpio_param / 32) + 1,
615 cfg->gpio_param % 32,
618 imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
620 gpio_requestf(cfg->gpio_param, "dio%d", i);
621 gpio_direction_input(cfg->gpio_param);
622 } else if (hwconfig_subarg_cmp(arg, "mode", "pwm")) {
623 if (!cfg->pwm_param) {
624 printf("DIO%d: Error: pwm config invalid\n",
629 printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
630 imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
636 if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
637 printf("MSATA: %s\n", (hwconfig("msata") ?
638 "enabled" : "disabled"));
640 if (gpio_cfg[board].rs232_en) {
641 printf("RS232: %s\n", (hwconfig("rs232")) ?
642 "enabled" : "disabled");
647 int misc_init_r(void)
649 struct ventana_board_info *info = &ventana_info;
653 /* set env vars based on EEPROM data */
654 if (ventana_info.model[0]) {
655 char str[16], fdt[36];
657 const char *cputype = "";
660 * FDT name will be prefixed with CPU type. Three versions
661 * will be created each increasingly generic and bootloader
662 * env scripts will try loading each from most specific to
665 if (is_cpu_type(MXC_CPU_MX6Q) ||
666 is_cpu_type(MXC_CPU_MX6D))
668 else if (is_cpu_type(MXC_CPU_MX6DL) ||
669 is_cpu_type(MXC_CPU_MX6SOLO))
671 env_set("soctype", cputype);
672 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
673 env_set("flash_layout", "large");
675 env_set("flash_layout", "normal");
676 memset(str, 0, sizeof(str));
677 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
678 str[i] = tolower(info->model[i]);
679 env_set("model", str);
680 if (!env_get("fdt_file")) {
681 sprintf(fdt, "%s-%s.dtb", cputype, str);
682 env_set("fdt_file", fdt);
684 p = strchr(str, '-');
688 env_set("model_base", str);
689 sprintf(fdt, "%s-%s.dtb", cputype, str);
690 env_set("fdt_file1", fdt);
691 if (board_type != GW551x &&
692 board_type != GW552x &&
693 board_type != GW553x &&
694 board_type != GW560x)
698 sprintf(fdt, "%s-%s.dtb", cputype, str);
699 env_set("fdt_file2", fdt);
702 /* initialize env from EEPROM */
703 if (test_bit(EECONFIG_ETH0, info->config) &&
704 !env_get("ethaddr")) {
705 eth_env_set_enetaddr("ethaddr", info->mac0);
707 if (test_bit(EECONFIG_ETH1, info->config) &&
708 !env_get("eth1addr")) {
709 eth_env_set_enetaddr("eth1addr", info->mac1);
712 /* board serial-number */
713 sprintf(str, "%6d", info->serial);
714 env_set("serial#", str);
717 sprintf(str, "%d", (int) (gd->ram_size >> 20));
718 env_set("mem_mb", str);
721 /* Set a non-initialized hwconfig based on board configuration */
722 if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
724 if (gpio_cfg[board_type].rs232_en)
725 strcat(buf, "rs232;");
726 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
728 sprintf(buf1, "dio%d:mode=gpio;", i);
729 if (strlen(buf) + strlen(buf1) < sizeof(buf))
732 env_set("hwconfig", buf);
735 /* setup baseboard specific GPIO based on board and env */
736 setup_board_gpio(board_type, info);
738 #ifdef CONFIG_CMD_BMODE
739 add_board_boot_modes(board_boot_modes);
742 /* disable boot watchdog */
743 gsc_boot_wd_disable();
748 #ifdef CONFIG_OF_BOARD_SETUP
750 static int ft_sethdmiinfmt(void *blob, char *mode)
757 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
761 if (0 == strcasecmp(mode, "yuv422bt656")) {
762 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
765 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
766 fdt_setprop_u32(blob, off, "vidout_trc", 1);
767 fdt_setprop_u32(blob, off, "vidout_blc", 1);
768 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
769 printf(" set HDMI input mode to %s\n", mode);
770 } else if (0 == strcasecmp(mode, "yuv422smp")) {
771 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
774 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
775 fdt_setprop_u32(blob, off, "vidout_trc", 0);
776 fdt_setprop_u32(blob, off, "vidout_blc", 0);
777 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
778 printf(" set HDMI input mode to %s\n", mode);
786 #if defined(CONFIG_CMD_PCI)
787 #define PCI_ID(x) ( \
788 (PCI_BUS(x->devfn)<<16)| \
789 (PCI_DEV(x->devfn)<<11)| \
790 (PCI_FUNC(x->devfn)<<8) \
792 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
798 sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
799 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
801 np = fdt_subnode_offset(blob, par, node);
804 np = fdt_add_subnode(blob, par, node);
806 printf(" %s failed: no space\n", __func__);
810 memset(reg, 0, sizeof(reg));
811 reg[0] = cpu_to_fdt32(PCI_ID(dev));
812 fdt_setprop(blob, np, "reg", reg, sizeof(reg));
817 /* build a path of nested PCI devs for all bridges passed through */
818 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
820 struct pci_dev *bridges[MAX_PCI_DEVS];
823 /* build list of parents */
824 np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
834 /* now add them the to DT in reverse order */
836 np = fdt_add_pci_node(blob, np, bridges[k]);
845 * The GW16082 has a hardware errata errata such that it's
846 * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
847 * of this normal PCI interrupt swizzling will not work so we will
848 * provide an irq-map via device-tree.
850 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
854 uint32_t imap_new[8*4*4];
855 const uint32_t *imap;
860 /* build irq-map based on host controllers map */
861 host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
863 printf(" %s failed: missing host\n", __func__);
867 /* use interrupt data from root complex's node */
868 imap = fdt_getprop(blob, host, "interrupt-map", &len);
869 if (!imap || len != 128) {
870 printf(" %s failed: invalid interrupt-map\n",
872 return -FDT_ERR_NOTFOUND;
875 /* obtain irq's of host controller in pin order */
876 for (i = 0; i < 4; i++)
877 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
880 * determine number of swizzles necessary:
881 * For each bridge we pass through we need to swizzle
882 * the number of the slot we are on.
888 while(d && d->ppar) {
889 b += PCI_DEV(d->devfn);
893 /* create new irq mappings for slots12-15
894 * <skt> <idsel> <slot> <skt-inta> <skt-intb>
895 * J3 AD28 12 INTD INTA
896 * J4 AD29 13 INTC INTD
897 * J5 AD30 14 INTB INTC
898 * J2 AD31 15 INTA INTB
900 for (i = 0; i < 4; i++) {
901 /* addr matches bus:dev:func */
902 u32 addr = dev->busno << 16 | (12+i) << 11;
904 /* default cells from root complex */
905 memcpy(&imap_new[i*32], imap, 128);
906 /* first cell is PCI device address (BDF) */
907 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
908 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
909 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
910 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
911 /* third cell is pin */
912 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
913 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
914 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
915 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
916 /* sixth cell is relative interrupt */
917 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
918 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
919 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
920 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
922 fdt_setprop(blob, np, "interrupt-map", imap_new,
924 reg[0] = cpu_to_fdt32(0xfff00);
927 reg[3] = cpu_to_fdt32(0x7);
928 fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
929 fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
930 fdt_setprop_string(blob, np, "device_type", "pci");
931 fdt_setprop_cell(blob, np, "#address-cells", 3);
932 fdt_setprop_cell(blob, np, "#size-cells", 2);
933 printf(" Added custom interrupt-map for GW16082\n");
938 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
939 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
943 unsigned char mac_addr[6];
946 sprintf(mac, "eth1addr");
949 for (j = 0; j < 6; j++) {
951 hextoul(tmp, &end) : 0;
953 tmp = (*end) ? end+1 : end;
955 fdt_setprop(blob, np, "local-mac-address", mac_addr,
957 printf(" Added mac addr for eth1\n");
965 * PCI DT nodes must be nested therefore if we need to apply a DT fixup
966 * we will walk the PCI bus and add bridge nodes up to the device receiving
969 void ft_board_pci_fixup(void *blob, struct bd_info *bd)
974 for (i = 0; i < pci_devno; i++) {
978 * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
979 * an EEPROM at i2c1-0x50.
981 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
982 (dev->device == 0x8240) &&
983 i2c_get_dev(1, 0x50))
985 np = fdt_add_pci_path(blob, dev);
987 fdt_fixup_gw16082(blob, np, dev);
990 /* ethernet1 mac address */
991 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
992 (dev->device == 0x4380))
994 np = fdt_add_pci_path(blob, dev);
996 fdt_fixup_sky2(blob, np, dev);
1000 #endif /* if defined(CONFIG_CMD_PCI) */
1002 #define WDOG1_ADDR 0x20bc000
1003 #define WDOG2_ADDR 0x20c0000
1004 #define GPIO3_ADDR 0x20a4000
1005 #define USDHC3_ADDR 0x2198000
1006 static void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
1008 int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
1011 fdt_delprop(blob, off, "ext-reset-output");
1012 fdt_delprop(blob, off, "fsl,ext-reset-output");
1016 void ft_early_fixup(void *blob, int board_type)
1018 struct ventana_board_info *info = &ventana_info;
1022 /* determine board revision */
1023 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1024 if (ventana_info.model[i] >= 'A') {
1025 rev = ventana_info.model[i];
1031 * Board model specific fixups
1033 switch (board_type) {
1036 * disable wdog node for GW51xx-A/B to work around
1037 * errata causing wdog timer to be unreliable.
1039 if (rev >= 'A' && rev < 'C') {
1040 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
1043 fdt_status_disabled(blob, i);
1046 /* GW51xx-E adds WDOG1_B external reset */
1048 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1052 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1053 if (info->model[4] == '2') {
1057 i = fdt_node_offset_by_compatible(blob, -1,
1060 range = (u32 *)fdt_getprop(blob, i,
1061 "reset-gpio", NULL);
1064 i = fdt_node_offset_by_compat_reg(blob,
1065 "fsl,imx6q-gpio", GPIO3_ADDR);
1067 handle = fdt_get_phandle(blob, i);
1069 range[0] = cpu_to_fdt32(handle);
1070 range[1] = cpu_to_fdt32(23);
1074 /* these have broken usd_vsel */
1075 if (strstr((const char *)info->model, "SP318-B") ||
1076 strstr((const char *)info->model, "SP331-B"))
1077 gpio_cfg[board_type].usd_vsel = 0;
1079 /* GW522x-B adds WDOG1_B external reset */
1081 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1084 /* GW520x-E adds WDOG1_B external reset */
1085 else if (info->model[4] == '0' && rev < 'E')
1086 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1090 /* GW53xx-E adds WDOG1_B external reset */
1092 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1094 /* GW53xx-G has an adv7280 instead of an adv7180 */
1095 else if (rev > 'F') {
1096 i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180");
1098 fdt_setprop_string(blob, i, "compatible", "adi,adv7280");
1099 fdt_setprop_empty(blob, i, "adv,force-bt656-4");
1106 * disable serial2 node for GW54xx for compatibility with older
1107 * 3.10.x kernel that improperly had this node enabled in the DT
1109 fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED);
1111 /* GW54xx-E adds WDOG2_B external reset */
1113 ft_board_wdog_fixup(blob, WDOG2_ADDR);
1115 /* GW54xx-G has an adv7280 instead of an adv7180 */
1116 else if (rev > 'F') {
1117 i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180");
1119 fdt_setprop_string(blob, i, "compatible", "adi,adv7280");
1120 fdt_setprop_empty(blob, i, "adv,force-bt656-4");
1126 /* GW551x-C adds WDOG1_B external reset */
1128 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1132 /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
1134 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1138 /* remove no-1-8-v if UHS-I support is present */
1139 if (gpio_cfg[board_type].usd_vsel) {
1140 debug("Enabling UHS-I support\n");
1141 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
1144 fdt_delprop(blob, i, "no-1-8-v");
1149 * called prior to booting kernel or by 'fdt boardsetup' command
1151 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1152 * - mtd partitions based on mtdparts/mtdids env
1153 * - system-serial (board serial num from EEPROM)
1154 * - board (full model from EEPROM)
1155 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1157 #define PWM0_ADDR 0x2080000
1158 int ft_board_setup(void *blob, struct bd_info *bd)
1160 struct ventana_board_info *info = &ventana_info;
1161 struct ventana_eeprom_config *cfg;
1162 static const struct node_info nand_nodes[] = {
1163 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1164 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1166 const char *model = env_get("model");
1167 const char *display = env_get("display");
1171 /* determine board revision */
1172 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1173 if (ventana_info.model[i] >= 'A') {
1174 rev = ventana_info.model[i];
1179 if (env_get("fdt_noauto")) {
1180 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1184 /* Update MTD partition nodes using info from mtdparts env var */
1185 puts(" Updating MTD partitions...\n");
1186 fdt_fixup_mtdparts(blob, nand_nodes, ARRAY_SIZE(nand_nodes));
1188 /* Update display timings from display env var */
1190 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1192 printf(" Set display timings for %s...\n", display);
1195 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1197 /* board serial number */
1198 fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
1199 strlen(env_get("serial#")) + 1);
1201 /* board (model contains model from device-tree) */
1202 fdt_setprop(blob, 0, "board", info->model,
1203 strlen((const char *)info->model) + 1);
1205 /* set desired digital video capture format */
1206 ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
1208 /* early board/revision ft fixups */
1209 ft_early_fixup(blob, board_type);
1212 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1213 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1216 sprintf(arg, "dio%d", i);
1219 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1224 printf(" Enabling pwm%d for DIO%d\n",
1226 addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
1227 off = fdt_node_offset_by_compat_reg(blob,
1231 fdt_status_okay(blob, off);
1235 #if defined(CONFIG_CMD_PCI)
1236 if (!env_get("nopcifixup"))
1237 ft_board_pci_fixup(blob, bd);
1241 * remove reset gpio control as we configure the PHY registers
1242 * for internal delay, LED config, and clock config in the bootloader
1244 i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-fec");
1246 fdt_delprop(blob, i, "phy-reset-gpios");
1249 * Peripheral Config:
1250 * remove nodes by alias path if EEPROM config tells us the
1251 * peripheral is not loaded on the board.
1253 if (env_get("fdt_noconfig")) {
1254 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
1259 if (!test_bit(cfg->bit, info->config)) {
1260 fdt_del_node_and_alias(blob, cfg->dtalias ?
1261 cfg->dtalias : cfg->name);
1268 #endif /* CONFIG_OF_BOARD_SETUP */
1270 int board_mmc_get_env_dev(int devno)